From: Marq Kole <marq.kole_at_.....>
Date: Mon Dec 04 2006 - 02:25:52 PST
All,
No I'm not going to answer this myself
:-)
It appears that the 2nd paramset in
the example is illegal as the LRM requires that the paramset body contain
at least one statement -- even if just an empty statement. So the following
paramset is legal:
paramset restest short;
parameter real r = 0 from [0:inf) exclude (0:inf); // Trick to select
only 0.
; // Empty statement
endparamset
If the verdict on paramsets for parameterless
modules is positive, I would suggest to change the syntax for this as well...
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Marq Kole <marq.kole@nxp.com>
Sent by:
owner-verilog-ams@server.eda.org
04-12-2006 11:12
To
"verilog-ams" <verilog-ams@server.eda-stds.org>
cc
Subject
paramset for a parameterless module?
Classification
All,
Can I use a paramset to select a parameterless module? Consider for instance
the following example:
paramset restest resistor;
parameter real r = 1k from (0:inf);
.r=r;
endparamset
paramset restest short;
parameter real r = 0 from [0:inf) exclude (0:inf); // Trick to select only
0.
endparamset
module short (a, b);
inout a, b;
electrical a, b;
analog V(a, b) <+ 0.0;
endmodule
In the LRM nothing is said about the relation between a paramset and the
module it is associated with, but it seems to suggest that the module needs
parameters...
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Tel: +31 40 27 49051, Fax: +31 40 27 44700, Mobile: +31 6 387 48 389
High Tech Campus 48 p.2.039, 5656 AE Eindhoven, The Netherlands
marq.kole@nxp.com, www.nxp.com
Received on Mon Dec 4 02:26:42 2006
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