Re: Verilog-AMS Committee Meeting Reminder - 7 Dec 2006

All,

I have not been able to provide an initial version of the AMS elaboration 
algorithm for section 7.8 (LRM 2.3, merged_hier.pdf); I propose to skip 
this agenda item until next call.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors










Sri Chandra <sri.chandra@freescale.com> 
Sent by:
owner-verilog-ams@server.eda.org
07-12-2006 13:24

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Verilog-AMS LRM Committee <verilog-ams@server.eda.org>
cc

Subject
Verilog-AMS Committee Meeting Reminder - 7 Dec 2006
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Hi all,

Date & Time: 7 Dec 2006, 9-10pm Pacific

Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

The new call times are:

09:00 PM Pacific   (Thursday)
11:00 PM Central   (Thursday)
Midnight Eastern
06:00 AM Eindhoven (Friday)
10:30 AM India     (Friday)
03:30 AM Adelaide  (Friday)

Agenda:

   * Review of algorithm proposal by Marq Kole for order of elaboration 
for resolution (requested as part of last committee meeting)

   * IDT solution proposed by Ken Kundert (document available at 
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/idt-proposal.pdf
)

cheers,
Sri
-- 
Srikanth Chandrasekaran
DTO Tools Development
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199