Re: Hierarchical reference questions

I'll propose that we add a keyword "useas"

useas ''discipline_name'' hier.net.reference.to.net;

with the "useas" declaration, the net would not Actually be coerced to this discipline, we'd get an
interface element instead.. 

One idea from tonights meeting.


 
Jonathan David
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----- Original Message ----
From: Graham Helwig <graham.helwig@astc-design.com>
To: Verilog-AMS Reflector <verilog-ams@eda.org>
Sent: Wednesday, December 6, 2006 11:46:38 PM
Subject: Hierarchical reference questions

Hello,

When simulating large mixed-signal design (containing transistors and 
gates) I have had the need to hierarchically reference an implicit net 
with the design. Also the resolved domain of the net is not known and 
even if it is known it may change from one simulation to the next.

I may of missed in the LRM, but is hierarchical referencing of an 
implicit nets allowed in the language?

If it is, then does the net need to be coerced to the same domain as the 
probe or does discipline resolution and ACMI resolves handle the 
resolution of the implicit net including any hierarchical references to 
that net?

For example:

    myDesign system(.....);
    electrical system.inst.inst.net;  // is this required?
    logic system.inst.net;            // is this required?
    analog $display("Value is %g.", V(system.inst.inst.net));
    initial $display("Value is %b.", system.inst.net);

Regards
Graham



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