RE: Hierarchical reference questions

From: Marq Kole <marq.kole_at_.....> Date: Thu Dec 07 2006 - 22:37:55 PST · This archive was generated by hypermail 2.1.8 : Thu Dec 07 2006 - 22:38:04 PST

    myDesign system(.....);

    //electrical system.inst.inst.net;  // not needed

    //logic system.inst.net;          
 // not needed

    analog $display("Value is %g.", V(electrical'(system.inst.inst.net)));

    initial $display("Value is %b.", logic'(system.inst.net));

FYI

Here is something from section 4.14 "Casting" of SystemVerilog
that

talks about how casting is done in that language.

> A data type can be changed by using a cast ( ' ) operation. In a

static cast, the expression to be cast

> shall be enclosed in parentheses that are prefixed with the casting

type and an apostrophe. If the

> expression is assignment

> compatible with the casting type, then the cast shall return the value

that a variable of the casting

> type would hold after being assigned the expression. If the expression

is not assignment compatible

> with the casting type, then if the casting type is an enumerated type,

the behavior shall be as

> described as in 4.15, and if the casting type is a bit-stream type,

the behavior shall be as

> described in 4.16.

Here is an example of how a real expression is cast to an int.

> int'(2.0 * 3.0) 

Thanks,

--Martin

-----Original Message-----

From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On

Behalf Of Jonathan David

Sent: Thursday, December 07, 2006 9:55 PM

To: Graham Helwig; Verilog-AMS Reflector

Subject: Re: Hierarchical reference questions

I'll propose that we add a keyword "useas"

useas ''discipline_name'' hier.net.reference.to.net;

with the "useas" declaration, the net would not Actually be coerced
to

this discipline, we'd get an interface element instead.. 

One idea from tonights meeting.

Jonathan David

j.david@ieee.org

jb_david@yahoo.com

http://ieee-jbdavid.blogspot.com

Mobile 408 390 2425

Work:

jbdavid@scintera.com

http://www.scintera.com

408 200-7024

----- Original Message ----

From: Graham Helwig <graham.helwig@astc-design.com>

To: Verilog-AMS Reflector <verilog-ams@eda.org>

Sent: Wednesday, December 6, 2006 11:46:38 PM

Subject: Hierarchical reference questions

Hello,

When simulating large mixed-signal design (containing transistors and

gates) I have had the need to hierarchically reference an implicit net

with the design. Also the resolved domain of the net is not known and

even if it is known it may change from one simulation to the next.

I may of missed in the LRM, but is hierarchical referencing of an

implicit nets allowed in the language?

If it is, then does the net need to be coerced to the same domain as the

probe or does discipline resolution and ACMI resolves handle the

resolution of the implicit net including any hierarchical references to

that net?

For example:

    myDesign system(.....);

    electrical system.inst.inst.net;  // is this required?

    logic system.inst.net;          
 // is this required?

    analog $display("Value is %g.", V(system.inst.inst.net));

    initial $display("Value is %b.", system.inst.net);

Regards

Graham

--

==========================================================

Graham Helwig

AMS Verification

Australian Semiconductor Technology Company (ASTC) Pty Ltd

Location: 76 Waymouth St, Adelaide, SA, 5000, Australia

Phone     +61-8-82312782

Moblie:   +61-4-03395909 

Email:    graham.helwig@astc-design.com

Web:      www.astc-design.com

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