From: Marq Kole <marq.kole_at_.....>
Date: Mon Dec 11 2006 - 04:21:03 PST
Kev,
If I read correctly the "light-weight"
a2d/d2a system functions work essentially as a cast. If the source type
is already of the same type as the target type, the cast is transparent,
as is the a2d/d2a function call.
The new thing Martin brought forth is
to (partially) automate this casting (in case of strobe arguments?). Just
like the cast is explicit, so are the a2d/d2a function calls. If this is
only for display tasks, I have no problem, but for more extensive uses
we need some more thinking...
For the portability issue: making it
part of the standard will also solve this! I agree that PLI has been around
much longer and that most AMS solutions on the market today support it,
but from the user's point of view (maybe an analog/mixed-signal user) PLI
is a much higher barrier than something that is part of the language. Moreover,
unless the PLI implementations of these light weight functions or at least
their behavior are somehow standardized as well, the defined behavior through
the standard will be much more reliable in inter-operability. Then, if
you standardize these functions behavior, why not make them part of the
standard anyway?
But maybe I'm redoing some of the "ages-old"
discussion here :-)
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Kevin Cameron <kevin@sonicsinc.com>
Sent by:
owner-verilog-ams@server.eda.org
08-12-2006 20:07
To
verilog-ams <verilog-ams@server.eda-stds.org>
cc
"Martin O'Leary" <oleary@cadence.com>
Marq Kole <marq.kole@nxp.com>
Subject
Re: Hierarchical reference questions
Classification
This problem was discussed ages ago, and a suggestion at the time was to
use "light-weight" a2d/d2a system functions to provide logic/voltage
values for display/verification purposes, e.g.:
initial $display("Value is %b.", $a2d(system.inst.net));
The $a2d function can be supplied by the user in regular Verilog through
PLI, so your testbench is more portable. If the net happens to be
digital the value just feeds through.
The implementation of the underlying a2d function should be provided by
the user in Verilog-AMS much the same way as a2d modules are - see
http://www.eda-stds.org/verilog-ams/htmlpages/tc-docs/issues/0018/index.html
Kev.
Martin O'Leary wrote:
> Marq,
> Yes that is what I am suggesting.
>
> However particularly in the case of;
> initial $display("Value is %b.", system.inst.net);
> Some form of automatic casting is also desirable so that users don't
> have to change pure-digital test benches to do AMS simulations.
>
> so that if system.inst.net becomes an analog net, that this reference
> is automatically cast to the default discrete discipline in order
to
> have an IE inserted.
>
> Thanks,
> --Martin
>
> ------------------------------------------------------------------------
> *From:* owner-verilog-ams@eda.org
> [mailto:owner-verilog-ams@eda.org] *On Behalf Of *Marq
Kole
> *Sent:* Thursday, December 07, 2006 10:38 PM
> *To:* verilog-ams
> *Subject:* RE: Hierarchical reference questions
>
>
> Martin,
>
> Instead of the proposed "useas" keyword would
you suggest that we
> can also fit the casting operation to our needs? So
for Graham's
> example:
>
> myDesign system(.....);
> //electrical system.inst.inst.net; //
not needed
> //logic system.inst.net;
// not needed
> analog $display("Value is %g.",
> V(electrical'(system.inst.inst.net)));
> initial $display("Value is %b.",
logic'(system.inst.net));
>
> As a way to handle OOMR I like this better than the
"useas" keyword.
>
> Cheers,
> Marq
>
>
> Marq Kole
> Competence Leader Robust Design
>
> Research
> NXP Semiconductors
>
>
>
>
>
>
>
>
>
> *"Martin O'Leary" <oleary@cadence.com>*
>
> Sent by:
> owner-verilog-ams@server.eda.org
>
> 08-12-2006 07:06
>
>
> To
>
"Jonathan David" <jb_david@yahoo.com>
> "Graham Helwig" <graham.helwig@astc-design.com>
> "Verilog-AMS Reflector" <verilog-ams@server.eda.org>
> cc
>
> Subject
>
RE: Hierarchical reference questions
> Classification
>
>
>
>
>
>
>
>
>
>
> FYI
>
> Here is something from section 4.14 "Casting"
of SystemVerilog that
> talks about how casting is done in that language.
>
> > A data type can be changed by using a cast ( '
) operation. In a
> static cast, the expression to be cast
> > shall be enclosed in parentheses that are prefixed
with the casting
> type and an apostrophe. If the
> > expression is assignment
> > compatible with the casting type, then the cast
shall return the
> value
> that a variable of the casting
> > type would hold after being assigned the expression.
If the
> expression
> is not assignment compatible
> > with the casting type, then if the casting type
is an enumerated
> type,
> the behavior shall be as
> > described as in 4.15, and if the casting type is
a bit-stream type,
> the behavior shall be as
> > described in 4.16.
>
> Here is an example of how a real expression is cast
to an int.
>
> > int'(2.0 * 3.0)
>
> Thanks,
> --Martin
>
> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org]
On
> Behalf Of Jonathan David
> Sent: Thursday, December 07, 2006 9:55 PM
> To: Graham Helwig; Verilog-AMS Reflector
> Subject: Re: Hierarchical reference questions
>
> I'll propose that we add a keyword "useas"
>
> useas ''discipline_name'' hier.net.reference.to.net;
>
> with the "useas" declaration, the net would
not Actually be coerced to
> this discipline, we'd get an interface element instead..
>
> One idea from tonights meeting.
>
>
>
> Jonathan David
> j.david@ieee.org
> jb_david@yahoo.com
> http://ieee-jbdavid.blogspot.com
> Mobile 408 390 2425
> Work:
> jbdavid@scintera.com
> http://www.scintera.com
> 408 200-7024
>
> ----- Original Message ----
> From: Graham Helwig <graham.helwig@astc-design.com>
> To: Verilog-AMS Reflector <verilog-ams@eda.org>
> Sent: Wednesday, December 6, 2006 11:46:38 PM
> Subject: Hierarchical reference questions
>
> Hello,
>
> When simulating large mixed-signal design (containing
transistors and
> gates) I have had the need to hierarchically reference
an implicit net
> with the design. Also the resolved domain of the net
is not known and
> even if it is known it may change from one simulation
to the next.
>
> I may of missed in the LRM, but is hierarchical referencing
of an
> implicit nets allowed in the language?
>
> If it is, then does the net need to be coerced to the
same domain
> as the
> probe or does discipline resolution and ACMI resolves
handle the
> resolution of the implicit net including any hierarchical
> references to
> that net?
>
> For example:
>
> myDesign system(.....);
> electrical system.inst.inst.net; //
is this required?
> logic system.inst.net;
// is this required?
> analog $display("Value is %g.",
V(system.inst.inst.net));
> initial $display("Value is %b.",
system.inst.net);
>
> Regards
> Graham
>
>
>
> --
> ==========================================================
> Graham Helwig
> AMS Verification
> Australian Semiconductor Technology Company (ASTC) Pty
Ltd
>
> Location: 76 Waymouth St, Adelaide, SA, 5000, Australia
> Phone +61-8-82312782
> Moblie: +61-4-03395909
> Email: graham.helwig@astc-design.com
> Web: www.astc-design.com
> ==========================================================
>
>
>
>
>
>
>
Received on Mon Dec 11 04:25:42 2006
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