Verilog-AMS committee meeting reminder (14 Dec 2007)

Hi all,

Date & Time: 14 Dec 2006, 9-10pm Pacific

Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

The new call times are:

09:00 PM Pacific   (Thursday)
11:00 PM Central   (Thursday)
Midnight Eastern
06:00 AM Eindhoven (Friday)
10:30 AM India     (Friday)
03:30 AM Adelaide  (Friday)

Agenda:

   * Review of algorithm proposal by Marq Kole for order of elaboration 
for resolution (requested as part of last committee meeting)

   * Resolution of using hierarchical reference for nets (digital vs 
analog context) for testbenches. Couple of proposals have been submitted 
  - using specific keyword vs casting syntax using in System Verilog

   * Any other queries on hierarchical references that is brought up 
during the call

   * IDT solution proposed by Ken Kundert document available at 
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/idt-proposal.pdf
     (We will do the document review if Ken joins into the call)

cheers,
Sri
-- 
Srikanth Chandrasekaran
DTO Tools Development
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199