Re: Elaboration algorithm proposal

Marq Kole wrote:
> (quoting Ken)
> > Presumably we would have the variables owned by a
> > particular analog block, but even with this there are issues.

When using a generate construct, one might like to have an array
variable where a the i'th element is "owned" by the i'th analog
block.  Keeping track of the owner by index will be a nuisance.

> > Consider
> > two analog blocks, b1 and b2, and two variables, v1 and v2. Assume that
> > v1 is owned by b1 and so can only be assigned in b1. Similarly, v2 is
> > owned by b2. Now assume that in b1 a value is assigned to v1 that
> > depends on the value of v2. Further assume that in b2 a value is
> > assigned to v2 that depends on v1. How does one reconcile the fact that
> > these two assignments are expected to occur simultaneously?
> 
> (from: http://www.eda-stds.org/verilog-ams/hm/1643.html)
> 
> To put the proposed example of Ken into code:
> 
> module test_multiple_analog_blocks (p, n);
>   inout p, n;
>   electrical p, n;
>   parameter real res = 1k from (0:inf);
>   parameter real cap = 1u from (0:inf);
> 
>   real r, c;
> 
>   analog
>     begin
>       c = cap;
>       I(p, n) <+ V(p, n)/r;
>     end
> 
>   analog
>     begin
>       r = res;
>       V(p, n) <+ idt(V(p, n)/c);
>     end
> 
> endmodule

That's not Ken's example.

module test_multiple_analog_blocks (in, o1, o2);
  inout in, o1, o2;
  electrical in, o1, o2;

  real a, b;

  analog
    begin
      a = b + V(in);
      I(o1) <+ a;
    end

  analog
    begin
      b = a + V(in);
      V(o2) <+ b;
    end

endmodule


-Geoffrey