Re: multiple analog blocks

Seems to me that it would be good to give the simulator the opportunity 
to evaluate internal variables from parameters post-elaboration and 
prior to actual transient simulation (if they are going to be constant 
for transient). If @initial_step doesn't do that (and it doesn't seem 
to), can we make it that digital initial blocks run before any analog 
processes starts, so that a "smart" compiler can work out what will be 
constant?

Kev.

Geoffrey.Coram wrote:
> Marq -
> I'm trying to stamp out the practice of using @initial_step.
> The reason it is there in some compact models is that the
> most "expensive" simulations are generally transient --  one
> doesn't run a million-transistor design through a dc sweep --
> and @initial_step works for that case, and is very helpful
> in some first-generation compilers (or interpreted V-A
> solutions).
>
> Many of the new compact models, including PSP, use the
> existing capability to name blocks, eg:
>   begin : initializeModel
>   end
> which some compilers (ADMS) can use as a crutch.  The
> commercial tools don't need this.  This capability already
> exists in the LRM and doesn't conflict with other uses of
> the "initial" keyword.
>
> If the analog initial block is provided, I think there
> will be some compilers that are lazy and don't look for
> other calculations to pull into the initialization.
> Having the analog initial block in the LRM will give the
> vendors an excuse to be lazy.  And when evaluating models,
> if someone says "model X runs 2x slower than model Y on
> simulator A" then this will be held against model X, even
> if the problem is simulator A.  So then the authors of
> model X will have to do the work of collecting all their
> initialization code.
>
> -Geoffrey
>
>
>
> Marq Kole wrote:
>   
>> Geoffrey,
>>
>> I share Martin's concerns on current (compact) modelling practices. What I see a lot of compact model developers do is to use @initial_step to perform some kind of initialization, under the mistaken assumption that this is the right (and only) place to do so. An analog initialization can provide a syntactically appealing place for those looking for a "standard" place to put their initializing code. In that sense the analog initialization is no more than some syntactic sugar.
>>
>> Why do you think it forces a particular coding style? I would definitely be against being forced to move all "initialization" code to an analog initialization block. In my opinion a compiler that optimizes named blocks on activity should work whether an analog initialization block is used or not -- consider that compiler optimization is not enforced in the language either, but it is a way compiler developers can offer more performce to their users. Considering (assuming?) there already are optimizing Verilog-A compilers, the advantage of an analog initialization block would be on the modeller's side.
>>
>> Cheers,
>> Marq
>>     
>
>