RE: multiple analog blocks

I agree that the term "const variable" is confusing, but there are
significant differences between const variables and
parameters/localparams in SystemVerilog.

 

Parameters are assigned values at elaboration time whereas const
variables get their values at simulation time. One result of this is
that parameters can be used in certain contexts where variables can not.
For example, to declare the bit-range of a vector.

 

One case where a parameter cannot be used in place of a const variable
is where the const variable is automatic, as in a re-entrant function or
task. In this case, the const variable can be assigned any expression
which would be legal if the variable were not declared with the const
keyword. So it can be a function of values of variables, just it cannot
be overwritten later.

 

Shalom

 

________________________________

From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Friday, December 22, 2006 1:33 AM
To: verilog-ams@server.verilog.org
Subject: Re: multiple analog blocks

 


Kev, 

A const variable declaration (isn't that an oxymoron) is essentially the
same as a localparam declaration. Both require an initialization and
localparams are already part of the language (even just the Verilog-A
subset). The only difference is that the places where localparams can be
declared are more restricted than those for variables.