RE: Verilog-AMS Committee Meeting Minutes - Jan 11 2007

There has been discussion recently in SV-BC on task/function inout and
output arguments: defaults, omitting them in t/f call, and using a
non-writable inout argument such as a constant. $random was brought as
an example that might serve as a precedent. There are several approaches
to user-defined tasks/functions, each with pros and cons.

Shalom

> -----Original Message-----
> From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com]
> Sent: Monday, January 15, 2007 2:59 PM
> To: Bresticker, Shalom
> Cc: VerilogAMS Reflector
> Subject: Re: Verilog-AMS Committee Meeting Minutes - Jan 11 2007
> 
> "Bresticker, Shalom" wrote:
> >
> > > The $rdist functions need some thought.  Per a recent
> > > e-mail on one of the SV lists, $random can be called
> > > without a seed (in which case the simulator sets up
> > > an internal variable to track it) -- but *cannot* have
> > > a parameter as a seed; this is different from what we
> > > have specified.
> >
> > [SB] To elaborate: $random specifies that the optional seed argument
> is
> > an inout variable of 32-bits. Since a parameter is a constant and
> cannot
> > be written, it does not qualify. Some simulators are lenient and
allow
> > it, but that is beyond the letter of the standard.
> 
> If the seed is optional, then simulators have been set up to
> automatically create a variable for storing the seed (and updating
> it each time $random is called).  It's not much of a stretch to say
> that, if the seed is a parameter (or literal constant), then the
> simulator should similarly create a variable for storing the seed,
> and initialize the variable using the constant value.
> 
> But, as you say, that is not presently part of any LRM.
> 
> -Geoffrey

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