Re: Verilog-AMS Committee Meeting Reminder - 25 Jan 2007

From: Marq Kole <marq.kole_at_.....>
Date: Wed Jan 24 2007 - 23:52:09 PST

All,

This is a retry - something went wrong with a message that I sent out last night.

I've asked Geoffrey to upload an initial version of my Multiple Analog Blocks document to the Verilog-AMS website. It is available at:

http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/Multiple_Analog_Blocks_v1.pdf

Unfortunately there is even less time for reviewing it before the conference call tonight/tomorrow-morning than I had originally anticipated.

In the document I've tried to look at the multiple analog blocks item from as many angles as possible. I've tried to set out a couple of restrictions and guidelines at the start of the document. For the issues identified I've tried to collect multiple options to later consider pro's and con's of each and give a reasonable preference, taking the guidelines as a reference. Most of the input is collected from the recent dicussions on the mailing list so you can all consider yourselves coauthor in that respect.

For those that are not able or willing to call into the telephone conference, do provide your feedback to the Verilog-AMS mailing list. I still expect a few angles that I've missed, or alternative solutions that are much more elegant than I've been able to come up with. If you'd rather not get involved in the discussions, I'd still welcome your comments and feedback - you can also email me directly.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors

Sri Chandra <sri.chandra@freescale.com> Sent by: owner-verilog-ams@server.eda.org 24-01-2007 13:32

To Verilog-AMS LRM Committee <verilog-ams@server.eda.org> cc Subject Verilog-AMS Committee Meeting Reminder - 25 Jan 2007 Classification

Hi all,

Date & Time: 25 Jan 2007, 9-10pm Pacific

Call-In Details:
 USA Toll Free Number: 877-346-8823
 USA Toll Number: +1-203-320-0407 (for intl)
 Participant Passcode: 602538

The call times are:

09:00 PM Pacific   (Thursday)
11:00 PM Central   (Thursday)
Midnight Eastern
06:00 AM Eindhoven (Friday)
10:30 AM India     (Friday)
03:30 AM Adelaide  (Friday)

Agenda:
  * Multiple analog blocks proposal from Marq Kole
  * Upwards hierarchical references (section 8.8.5) raised by Kevin
  * Continue review on Chapter 10 documentation

Regards,
Sri
--
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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This message has been scanned for viruses and
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believed to be clean. Received on Wed Jan 24 23:52:30 2007