RE: Verilog-AMS Committee Meeting Reminder - 25 Jan 2007

This is actually not clear.

1364-2005, 3.8, says,

"With the proliferation of tools other than simulators that use Verilog
HDL as their source, a mechanism is included for specifying properties
about objects, statements, and groups of statements in the HDL source
that can be used by various tools, including simulators, to control the
operation or behavior of the tool. These properties shall be referred to
as attributes. This subclause specifies the syntactic mechanism that
shall be used for specifying attributes, without standardizing on any
particular attributes."

Shalom

> In 3.1.1, option 2 suggests use of an attribute for marking
> race conditions.  In 1364, attributes are not supposed to
> be used for anything that can change simulation results;
> they are in some sense "hints" to be used to help the
> simulator perform more efficiently.  I think your option 2
> would violate this definition.

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