Oh, yes. At most, an attribute would define an optional tool-dependent behavior. I was just saying that it was not clear to me that an attribute could not define an optional simulator behavior instead of the default behavior. Shalom > -----Original Message----- > From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com] > Sent: Thursday, January 25, 2007 3:50 PM > To: Bresticker, Shalom > Cc: verilog-ams > Subject: Re: Verilog-AMS Committee Meeting Reminder - 25 Jan 2007 > > Somewhere in 1364, I thought I read something about tools being > allowed to ignore any attributes that they don't recognize/ > support, and this should not change simulation results. > > In Marq's proposal, if one does not mark a potential race > condition with the attribute, the simulator should error out > when the race condition is detected. > > -Geoffrey > > > "Bresticker, Shalom" wrote: > > > > This is actually not clear. > > > > 1364-2005, 3.8, says, > > > > "With the proliferation of tools other than simulators that use > Verilog > > HDL as their source, a mechanism is included for specifying properties > > about objects, statements, and groups of statements in the HDL source > > that can be used by various tools, including simulators, to control > the > > operation or behavior of the tool. These properties shall be referred > to > > as attributes. This subclause specifies the syntactic mechanism that > > shall be used for specifying attributes, without standardizing on any > > particular attributes." > > > > Shalom > > > > > In 3.1.1, option 2 suggests use of an attribute for marking > > > race conditions. In 1364, attributes are not supposed to > > > be used for anything that can change simulation results; > > > they are in some sense "hints" to be used to help the > > > simulator perform more efficiently. I think your option 2 > > > would violate this definition. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 25 05:53:41 2007
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