Re: Potential Contributions

Muranyi, Arpad wrote:
> Can't resist not to chime in...
>  
> Since when are physical devices ideal?  I.e. when will
> a real life voltage source have zero impedance?  Let
> me know if you see one, I would like to get one of those.
Superconductors.

In particular: Josephson Junction logic circuits rely on switching the 
state of a SQUID from superconducting to resistive states; in the 
superconducting state the SQUID is an ideal 0V source - it switches to 
resistive when you drive too much current through it or apply a large 
enough magnetic field.

Here are some links :

 http://swordfish.eecs.berkeley.edu/markj.www/COSLGate.html
 http://books.google.com/books?id=8_mngdg77sUC&pg=PA300&lpg=PA300&dq=josephson+junction+%22voltage+state%22+logic&source=web&ots=pFt5FKyaFe&sig=4SvM-ZtRuw77AFK5hdBqNPKsZ3s#PPP1,M1
>  
> Also, believe it or not, 0.3+0.6 is NOT equal 0.9!!!
> Try this in Matlab:  isequal(0.3+0.6,0.9), the answer
> will be a FALSE.  The point is that if the voltage
> sources are defined using equations, you may get
> inequalities without noticing...
I'm aware of that, but the cases I'm considering (as likely) are those 
where some identical components have been instantiated in parallel and 
the voltage is more likely derived from parameters  (or zero for 
switches), so rounding error mismatch is not likely.

Kev.
>  
> I would join the camp that doesn't mess with the ideal
> sources with additional series resistors.  In this
> day of age, when we are modeling "shorts" as transmission
> lines and argue over how good or bad the lossy T-line model
> is depending on its algorithms, I would think that a decent
> engineer should not expect that two ideal sources connected
> in parallel would be a correct netlist.
>  
> I got curious about the inductor case.  Yes, HSPICE will
> bail out with an error if I connect a V source and an
> inductor in parallel.  But only if I use an ideal inductor!
> Once I define its resistive parasitics like this:
>  
> L1  n1 n2 L=1nH R=0.001
>  
> it will work without an error.  This is what I call being
> in agreement with physics...
>  
> Arpad
> =============================================================
>
> ------------------------------------------------------------------------
> *From:* owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] *On Behalf Of *edaorg@v-ms.com
> *Sent:* Tuesday, January 30, 2007 6:49 PM
> *To:* verilog-ams
> *Cc:* Geoffrey.Coram
> *Subject:* Re: Potential Contributions
>
> Geoffrey.Coram wrote:
>> Kevin Cameron wrote:
>>   
>>> According to Marq at least one simulator company has it's simulator
>>> handling this with sharing the current across the sources, I'll presume
>>> that they had some motivation for doing so.
>>>     
>>
>> Since one simulator actually allowed unequal voltage sources to
>> be placed in parallel, it is almost certain that this simulator
>> indeed did place GMIN-like resistors in series with the voltage
>> sources.
>>
>> I would guess the motivation was along the lines:
>> Customer: hey, why can't I do this?  The voltages are equal!
>>   What a dumb simulator.
>> AE: OK, I'll ask R&D to fix it.
>>
>> and R&D might not have ever seen the test case, which might
>> have had exactly the sorts of problems Ken mentions.
>>   
> I'm with the "customer" - if the physics/electronics makes sense it 
> should be allowed in the HDL, and the simulator should make it's best 
> effort to handle it.
>>   
>>> We need a definition of the behavior of parallel potentials for the LRM,
>>> my view is that they should be allowed as long as the potential is
>>> exactly the same and the current will be split evenly across the
>>> potentials (and the user gets a warning). If you disagree propose
>>> something different.
>>>     
>>
>> As Marq pointed out, the potential is quite likely to be
>> not exactly equal: 1/1/3 versus 3.  I've also seen cases where
>> (on Intel machines) one floating-point number is stored in
>> an 80-bit register in the CPU and compared to a 64-bit number
>> in the cache, and they don't match in those extra bits.
>>   
> Interesting, but I'd bet 0.0 == 0.0 will always work. Floating point 
> numbers in Verilog are all supposed to be 64-bit IEEE, so getting a 
> mismatch with an 80-bit register would be something for the compiler 
> writers to fix.
>
> Kev.
>> -Geoffrey
>>   
> ------------------------------------------------------------------------
>
> mailto:dkc@grfx.com <mailto:dkc@grfx.com>
>
> -- 
> This message has been scanned for viruses and
> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is
> believed to be clean. 


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.