Re: Alternative text for 8.8.5: Vesrsion 2

From: Jonathan David <j.david_at_.....>
Date: Thu Feb 01 2007 - 13:12:31 PST
I'd find that confusing as I don't expect a signal name to be in ANYTHINGS hierarchical path.. 
BUT that may ALSO guarantee that there is no name conflict.. 
(which the __ doesn't quite do..) 

 
Jonathan David
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----- Original Message ----
From: Kevin Cameron <kevin@sonicsinc.com>
To: Verilog-AMS LRM Reflector <verilog-ams@eda.org>
Cc: Kevin Cameron <kevin@sonicsinc.com>
Sent: Thursday, February 1, 2007 12:55:08 PM
Subject: Alternative text for 8.8.5: Vesrsion 2




  




Thinking about it I don't like the "__", I'd rather have a ".", gives
tools the opportunity to let you browse into the signal as a scope and
list what's there.



Alternative text for 8.8.5 (8.8.5.1 stays the same):




Instance names for auto-inserted instances
Parameters of auto-inserted connect instances can be set on an
instance-by-instance basis with the use of the defparam statement. This
requires predictable instance names and instance
paths for the auto-inserted modules.



In both the merged and split cases the connect module instance is
located in the nearest parent of the analog or digital
blocks using the connect module (the location of the contributions,
drivers or receivers), e.g. in the case where those blocks
are in one module the connect module instance will be a child of that
module. In the split case the connect module instance is only
associated with one block so it is automatically the child of that
block's module.



The instance name of the connect module is made
up from the name of the
signal being connected in the module which is parent to the connect
module instance (which need not be a port), and the name of the connect
module concatenated with a double dot ".", e.g. for signal
"mixed" in module "top" with a connect module "d2a" instantiated in it
the connect module path is:


top.mixed.d2a

  




Comments?



Kev.




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Received on Thu Feb 1 13:12:52 2007

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