To give some context to the other discussion on connect module
instantiation paths, here's a proposal for connecting up things like
power.
Rationale:
Digital design descriptions (Verilog) usually lack power supply
information, so a design hierarchy mixing Verilog-AMS and Verilog
modules needs a way to connect power signals from lower level
(analog/connect) modules to definitions up the hierarchy when the
immediate parent does not connect them. Connect modules need to connect
into the local power and substrate for accurate modeling but have no
port mechanism to support such connection.
Current SoC designs include large amounts of power management,
including varying back-bias and being able to turn off power to
sections of a chip, and these features need to be modeled.
Proposals:
1. Default Connection Statement
If a signal is in the port list or is marked as i/o (input, output or
inout) it can be given a default connection, the syntax being:
default <signal or port> = <connect expression>;
If no direct port connection is made to the signal it is connected as
indicated by the <connect expression>. It would be an error for
<connect expression> to be invalid (e.g, a non existant OOMR).
The connection behaves the same as a normal port of the module with
respect to connect module insertion, e.g. if the connection is for a
power supply that is gated in a digital module and the local reference
is analog a connect module would be inserted automatically. This may
mean that connect module instances are parents to other connect module
instances.
2. Upward Hierarchical Reference Operator
The operator "^." can be used to find an object in the direct parent
hierarchy. E.g. in the following module the signal
vdd will be
connected to the first occurrence of the signal
vdd in an
instance in the hierarchy above it (searching upward):
module foo(a,b,c);
input a,b;
output c;
input substrate; // not an explicit port
default vdd = ^.vdd;
...
endmodule
Notes:
The upward operator is required because normal hierarchical references
need an instance/block name as part of the reference (e.g.
power.vdd),
so won't allow connection into a parent without knowing the parent's
name.
The <connect expression> could be something complex like:
^.vdd or power.vdd
- that would allow a straight up search for a vdd, and if you hit the
top without finding it you look for it in an instance called power,
that way you can patch up a design by adding top level modules to catch
the dangling implicit signals.
Comments?
Kev.
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Received on Fri Feb 2 10:57:43 2007