RE: Implicit connections [corrected]

I had sent the previous mail on this to Gordon V. of Mentor.
These were his comments:

"Thanks for sending this to me.

I don't have any technical issues with "^." but I'm not sure that really
is the approach that I would like when thinking about power connections.

We've had some discussions internally here with respect to power
modeling (in the digital world of power enables not in the AMS
world) and I've been suggesting that we actually have an alternate way
of specifying "virtual" port connections via some variant of a
configuration.

I don't really like having "vdd" in the example not showing up in the
port list at all.  Particularly once one considers things like "external
module" and similar, this hides too much and may be a real problem for
some implementations (though likely not ModelSim).  I think that
something like "virtual input vdd = .vdd"
in an ansi port list would be a reasonable approach.  I would like to
see this restricted to ansi ports since there already is some confusion
about what is permitted in which parts of a non-ansi port list.

This is all just my opinion and likely doesn't mean anything in terms of
where Mentor might end up."

Shalom


> -----Original Message-----
> From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-
> ams@server.eda.org] On Behalf Of edaorg@v-ms.com
> Sent: Sunday, March 11, 2007 9:05 PM
> To: Verilog-A Reflector
> Subject: Re: Implicit connections [corrected]
> 
> 
> Added the power connection proposal to Mantis -
> 
> http://www.eda.org/mantis/bug_view_page.php?bug_id=0001754
> 
> Kev.

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