RE: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007

Shalom,
I am now aware of this (I read this section of 1800 last night). My
understanding is that these tasks are part of the assertions
functionality in SV and hence not appropriate to use in Verilog-AMS at
this point.

Please confirm.
Thanks,
--Martin 

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Wednesday, March 14, 2007 8:29 AM
To: Martin O'Leary; verilog-ams
Subject: RE: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007

Are you aware of the SystemVerilog run-time tasks of those names (see
1800-2005 17.2, 22.7).

There is also a proposal in 1800 to add similar compile/elaboration-time
tasks.

> * Add $error, $warning or maybe $fatal to support bad models that are 
> not detected until simulation time.
>   - $fatal - idea it reject current solution but it would be clean 
> termination.

Shalom

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