sent from the wrong address Jonathan David j.david@ieee.org jb_david@yahoo.com http://ieee-jbdavid.blogspot.com Mobile 408 390 2425 Work: jbdavid@scintera.com http://www.scintera.com 408 636-2618 ----- Forwarded Message ---- From: Jonathan David <jb_david@yahoo.com> To: Kevin Cameron <kevin@sonicsinc.com> Sent: Friday, March 23, 2007 11:27:31 AM Subject: Re: Connect module name/placement issue As currently defined (in the implementation I'm using).. the module in which the port is declared, is where the Power, ground (I STILL want CROSS) sensitivity is also defined.. so this is (I think) the 'down' side as defined by Kevin.. Except: if the power and ground sensitivity's are NOT defined in that module, I'm not sure there is a way for the connect module to resolve any inherited connection at all.. it just has to look to a default global net I think. By the way Cross sensitivity would give you access to the analog side net of the cross sensitive node as well as the node you are doing a connect module for.. I documented the behavior I want in my BMAS paper last year.. but no vendor seems ready to offer it to me yet. Jonathan David j.david@ieee.org jb_david@yahoo.com http://ieee-jbdavid.blogspot.com Mobile 408 390 2425 Work: jbdavid@scintera.com http://www.scintera.com 408 636-2618 ----- Original Message ---- From: Kevin Cameron <kevin@sonicsinc.com> To: Verilog-AMS LRM Reflector <verilog-ams@eda.org> Sent: Friday, March 23, 2007 10:38:41 AM Subject: Re: Connect module name/placement issue Just to recap: say we have a design instance hierarchy - Top | Middle | ------------- | | | | D1 R1 D2 R2 Say modules D1 and D2 have drivers and R1 and R2 receivers on the same net, so connect modules will be inserted. If the module "middle" routes power differently to D1 and D2 (e.g. some power gating) then you want the auto inserted module to pick up Vdd (say) for the D1 D2A in D1 and the D2 D2A in D2. The module "middle" may have a signal Vdd coming from top but will explicitly feed a gated (say) VddD1 to D1.Vdd and VddD2 to D2.Vdd. If the connect modules are instantiated in "middle" then a hierarchical upward search for "Vdd" will find the feed from top not the feed to D1 or D2. It is therefore desirable that the D2As are instantiated on the down side of the ports they are associated with, otherwise the search algorithm for hooking up "inherited" signals isn't going to be the same for regular and connect module instances (if it is going to work correctly). Kev. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Mar 23 11:49:11 2007
This archive was generated by hypermail 2.1.8 : Fri Mar 23 2007 - 11:49:15 PDT