Re: array parameters overrides

This should be an error. Same sort of error that would occur if you 
assigned the wrong size array to an array parameter.

parameter real P[0:2] = {1,2}; // error need array of size 3.

I just took for granted that assigning wrong size arrays, accessing 
arrays out of bounds etc. would generate errors.

Dave

Marq Kole wrote:
>
> All,
>
> In the Verilog-AMS 2.2 LRM there is nothing specified about overriding 
> array parameters; also in IEEE 1364-2005 nothing is mentioned on this 
> item.
>
> Considerthe following Verilog-A code:
>
> module map(a, b);
>   inout a, b;
>   electrical a, b;
>   parameter real ap[0:3] = { 0.0, 0.707, 1.0, 1.414 };
>
>   genvar i;
>
>   analog
>     for (i = 0; i <= 3; i = i + 1)
>       $write("ap[%d] = %g\n", i, ap[i]);
>
> endmodule // map
>
> module test_map(a, b);
>   inout a, b;
>   electrical a, b;
>
>   // overriding array length == 1
>   map #(.ap({ 1.2 })) X1 (a, b);
>   // overriding array length == 5
>   map #(.ap({ 3.1415, -1.01, 2.2u, 1e-9, 10.0 })) X2 (a, b);
>
> endmodule // test_map
>
> What would happen when the compiler/interpreter encounters the 
> instantiations X1 and X2? I could not find any reference in the 
> standard documents. To prevent ambiguity in the various simulators I 
> suggest that the elaboration is defined, for instance in section 7.2 
> in the Verilog-AMS LRM and/or in section 12.2.2 in IEEE 1364-2005.
>
> Personally, I would expect an error to occur for both instantiations, 
> essentially signalling a mismatch in length between the overriding and 
> overridden arrays.
>
> Cheers,
> Marq
>
>
> Marq Kole
> Domain Leader Robust Design
>
> Research
> NXP Semiconductors
>
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-- Design Technology (Austin)
-- Freescale Semiconductor
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