Verilog-AMS Committee Meeting - 19th April 2007

Date & Time: 12 April 2007

Call-In Details:
    USA Toll Free Number: 877-346-8823
    USA Toll Number: +1-203-320-0407 (for intl)
    Participant Passcode: 602538

The call times are:

06:30 am  US Pacific
08:30 am  US Central
09:30 am  US Eastern
15:30 pm  Eindhoven
19:00 pm  Noida
23:00 pm  Adelaide


Agenda for the call:
   - Updated chapter 7 based on the multiple analog block that has been 
proposed and discussed (Marq Kole)

Geoffrey also mentioned that it will be good to specify the list of 
future proposals and outstanding discussion documents, which I feel is a 
good idea and I have bulleted the same here.

Future discussion points for LRM 2.3:
   - Modified idt() analog operator proposal (Ken Kundert)
   - Proposal on ACMI and changes related to support for multiple power 
domains (Kevin Cameron); Cadence is also planning to submit a proposal 
on this problem which looks at the backward compatibility issues (Martin 
O'leary)
   - Updating examples on the Verilog-AMS website (Oskar Leuthold, 
Synopsys & Marq Kole, NXP)
   - $table_model proposal on chapter 10 (Patrick, Tiburon)
   - LRM 2.3 edits of chapter 8 (I think this is Dave/FSL, I need to 
check) & chapter 9 (Junwei Hou, Cadence)
   - Annexures (No assigned owners yet for this apart from the ones that 
Graham worked on)

cheers,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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