All,
Here are the meeting minutes of the
Verilog-AMS Committee Meeting of 19 April 2007
present:
Martin O'Leary - Cadence
Patrick O'Halloran - Tiburon
Geoffrey Coram - Analog Devices
Dave Miller - Freescale
Graham Helwig - FSTC
Marq Kole - NXP
agenda:
- Updated chapter 7 based on the multiple
analog block that has been proposed and discussed (Marq Kole)
minutes:
An update (version 4) of the Multiple
Analog Blcoks document was posted on the Verilog-AMS website, containing
updates to the previous version as discussed during last weeks conference
call.
After initially discussing the changes
that had to be made to the draft LRM 2.3 for multiple analog blocks there
was a growing unease amidst the participants about the support of concurrent
analog blocks. It was felt that there were too many unknowns still, in
particular regarding the concurrent assignment and variable acces for module-level
variables in multiple concurrent analog blocks. There was a consensus that
multiple concurrent analog blocks is a step too far for the current LRM.
Instead it was considered that the main
purpose for multiple analog blocks in LRM 2.3 is to support the new generate
construct and that it would be best to state that the behavior of multiple
analog blocks would be defined by assuming that they had been concatenated
in the order they appear in the module. This will still allow implementors
to support concurrent evaluation as long as the behavior in that case is
similar to what would happen if they were concatenated.
The reason was actually that the multiple
analog blocks discussion document showed many areas that would be problematic
to get consistent behavior for concurrent analog blocks. By defining the
behavior in this way, the generate construct will work; there will be no
limitations on things that can be modelled in the current language. The
members present in the call felt that we should be proceeding cautiously.
The driver for concurrent analog blocks will most likely come from the
ability to offer improved performance based on sensitivity lists, but that
area is still too unclear to base a standard on right now.
As it is the impact of multiple analog
blocks on the LRM text will be quite modest.
- based on the discussion results and
the decisions taken, the following will now be done:
* Marq will make a new update
of Section 7 of the LRM 2.3 to reflect the decisions, to be discussed next
week.
* Marq will propose changes for
a new update of Section 6 of the LRM 2.3 to the section owner (Sri) to
reflect the decisions, to be discussed next week.
For the next call it was suggested by
Geoffrey that we discuss the examples on the Verilog-AMS website.
Changes to the descriptions of the atan2
and mod built-in math functions as reported by Paul Floyd will be made
to the draft section 4 (merged_expr) document.
Geoffrey will update section 3 (merged_datatype)
with the string variable as discussed in the review of section 11.
next call:
April 26, 2007, regular call times
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Received on Fri Apr 20 05:05:38 2007