Minutes of Verilog-AMS call: 26 April 2007

Hi all,

Please find attached the minutes from the Verilog-AMS committee call

Date: 26 April 2007

Attendees:
Martin O'leary, Cadence
Dave Miller, Freescale
Patrick O'Halloran, Tiburon
Marq Kole, NXP
Geoffrey Coram, Analog Devices
Sri Chandra, Freescale


Verilog-AMS example donations:
   - The examples sent by Marq Kole are planned to be uploaded on to the 
Verilog-AMS website once the comments mentioned below are addressed
   - Patrick (Tiburon) mentioned that they can possibly donate the 
"spice3-like" testbenches that go along with these examples. The spice 
testbenches include the .hdl statement to include the verilog-ams 
instances. He will confirm this.
   - It was decided to have one spice testbench per verilog-a/ams file
   - All pure analog files will have the extension of .va and mixed 
signal files (having analog and digital behavior) will have extensions 
of .vams
   - If the analog model requires a noise or an ac simulation the 
appropriate analysis will be invoked through the spice testbench.
   - Synopsys also have worked on set of Verilog-AMS examples that was 
originally got from Accellera. There is a possibility of this also being 
donated. It was unclear whether the examples are from the Verilog-AMS 
website examples or they were LRM examples. If there is a donation from 
synopsys this will be discussed for inclusion into the website.

Corrections on the examples:
   - Some of the examples use analog operators (and contributions) 
within cross events which is not as per the standard. Marq is going to 
check these and move the contribution and transition operator outside 
the events.
   - Examples use "generate" syntax which has been deprecated. These 
need to be changed to "for" loop syntax.
   - Some examples use nested "for" loop within "generate" loop with the 
same genvar usage. This needs to be addressed.
   - Marq is going to put Accellera copyright notices for each of the 
examples.

Review of Section 3.2 (strings)
   - Geoffrey has modified this section to include the string datatype 
from system verilog.
   - typo on page-31 section 3.3.4 on the default word
   - need to allow strings to be initialized through a string parameter.
   - check the fonts on 'Str'.
   - This needs to be reflected in the Verilog-AMS BNF


Next call:
   - We will review $table_model proposal from Patrick (Tiburon).

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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