Kevin wrote: >The problem is that if you take an analog block which is in one module >and another in another module that contribute to the same nodes, then >the behavior can change if you put them in the same module (but >otherwise connect them the same). My view is that is a subtlety that >most engineers are not going to appreciate and it will become a source >of bugs. Any time you change the connectivity patterns you can get this case.. in software, simulation or hardware. I'm not so convinced today that this is a big problem. I guess this is why this discussion migrated from switch branches - because thats exactly the type of model that would work at standalone module level, but not as an analog block.. ie the case where 1 block sets the voltage to zero - and another block adds something to that "zero" to make it non-zero.. while they seem kind of cool at first, I rarely found good use for them.. mainly because even my "good" switches in silicon have several ohms (often a hundred or more) in resistance.. and I don't do much above that level these days.. do you have other examples? of something that causes a problem at the block level. Here is one.. Several switches combined in parallel to from a resistive DAC.. designer writes each one as V(in,out) <+ I(in,out)*(bit?Rdac:10K*Rdac); instead of I(in,out) <+ V(in,out)*(bit?Gdac:Gdac/10K); (yeah, I'd recommend doing a transition, and doing it on the EXPONENT of the resistor not the value itself.. ) back to the case in point.. If I write each switch as its own element, each one creates ITS OWN (in,out) branch , and so everything connects in parallel. if you create each as an analog block in a one module, you get one branch and all the voltages add in series.. you can easily get around this by explicitly creating a branch per switch, or implicitly by casting the output in terms of a current. 1. other than the ability to put them in their own blocks, THIS PROBLEM EXISTS in VERILOG-A NOW.. !!! 2. Analog Modeling Guys DO think about this kind of stuff.. Its their bread and butter!! 3.. Its something that could be a great application of a linting tool.. -CAUTION: Voltage contributions to branch A,B exist in multiple analog blocks, they will add in series.. I don't know if thats such a good example since they all contribute resistively to a single node pair, so they will have to be evaluated in the SAME matrix, on the same timestep, so there would be little value to having them in separate blocks. assuming they add in series, and that different blocks are evaluated on different timesteps.. (lets say its a DAC - with a voltage output (not resistive) with each bit being in its own block, and evaulated on its own timesteps.. then the total output would be the sum of all the contributions from their last timestep linearly interpolated to their next one (in the same way a voltage probe in an always block is evaluated) again I don't think I've thought of all the implications.. but Voltage(potential) drivers to a branch (one path between a node pair) should add in series, while current drivers should add in parallel.. would there be a way to protect a branch so that oomrs can't contribute to it? more useful at the model (ie analog block) level than in the design interconnect.. ie allow oomr contribution to a branch only if the branch is declared at the module - not block level.. ? guess It's time for me to get out the front door. Jonathan Jonathan David j.david@ieee.org jb_david@yahoo.com http://ieee-jbdavid.blogspot.com Mobile 408 390 2425 Work: jbdavid@scintera.com http://www.scintera.com 408 636-2618 ----- Original Message ---- From: Kevin Cameron <kevin@sonicsinc.com> To: Verilog-A Reflector <verilog-ams@eda.org> Cc: Ken Kundert <ken@designers-guide.com> Sent: Monday, April 30, 2007 10:02:43 AM Subject: Re: Contributions (was Re: disallow distributed switch branches) Ken Kundert wrote: > edaorg@v-ms.com wrote: > >> Ken Kundert wrote: >> >>> All, >>> One of the original reasons why we went with the contribution >>> operator with its accumulating nature as opposed to a equality operator >>> when the language was first designed was that it neatly addressed the >>> question of "what happens if you apply it more than once to the same >>> branch". There are two choices if you use an equality operator: >>> 1. it is an error >>> 2. one wins >>> Neither seemed like a very good alternative, but in the case of OOMRs in >>> particular it was decided that neither was desirable. Consider each case: >>> 1. if it is an error to give a value to a branch more than once, then >>> once a branch is given a value in a module, then it could never be given >>> a value via an OOMR. Since it is likely that any branch that one might >>> want to give a value to via an OOMR would already have a value, this >>> seemed like too big a restriction. >>> 2. if only one wins when two values are given to a branch, how is it >>> decided which value wins, particularly if both values are being given >>> via OOMRs. >>> >>> >> That's what the solver is for, it's not some kind of race condition. >> > > The situation is ambiguous. There are two equations when there should > only be one. With the accumulating nature of the contribution operator > we define how they should be combined. If we remove the accumulating > nature, then we must define some other way for the ambiguity to be resolved. > Are you talking about the accumulating nature of the "<+" operator or just branches in general? > >>> Since the accumulating nature of the contribution operator was added to >>> the language specifically to support OOMRs, it seems odd that we are now >>> considering stripping this feature, but only for OOMRs. Has there been >>> some issue with the contribution operator and OOMRs? I have heard people >>> voice an opinion that they would prefer that it be changed, but nobody >>> has pointed out any real problems with the way it works now or what >>> significant new capability would be gained if a change were made.assignments >>> >> [Don't recall the accumulating nature of the operator having much to do >> with OOMRs myself, I suspect the OOMR stuff was pretty much an >> afterthought.] >> >> The current behavior is inconsistent in that if you wire something up >> with OOMRs vs using ports then you can get different behavior. To >> someone with a good understanding of electronics and digital Verilog >> it's not at all obvious that an OOMR potential contribution will add in >> series with other potential contributions to a branch - the obvious >> behavior would be that it was in parallel (as with using ports). >> > > I am at a loss to understand why it is a problem that contributions do > not behave the same as port connections, especially since doing so would > make OOMR contributions inconsistent with in-module contributions. > I would differentiate "in-module" and "in-block", this discussion sprang out of issues related to having multiple analog blocks in a module. While I have no real issues with the "<+" in-block behavior, I don't see the logic in extending it to in-module (for multiple blocks) or to OOMRs. The problem is that if you take an analog block which is in one module and another in another module that contribute to the same nodes, then the behavior can change if you put them in the same module (but otherwise connect them the same). My view is that is a subtlety that most engineers are not going to appreciate and it will become a source of bugs. > >> IMO the easiest way out of the problem is to deprecate "<+" as an >> operator for OOMRs, and use a new operator which is explicitly indicates >> that the contribution is in series or parallel (e.g. <++,<=). >> > > Again, we seem to be proposing changes for the sake of change. Is there > a documented problem we are trying to solve? > Yes. "<+" on OOMRs gives a different behavior than regular port connection, and there is no operator to get the same behavior as port connection. I don't believe the average user will be aware of the difference in behavior so that usage should be discouraged. I case I'd consider possible is where in some higher level of a design you decide you need to short some connections on a pcb so you do: V(a.b.x,a.b.y) <+ 0.0; If someone else had decided to add noise on that branch a level down - V(b.x,b.y) <+ noise_fn(); Then do you have a) failure because you can't drive two different voltages, or b) the noise, or c) 0 Volts. I think a) is the correct behavior for the simulator, b) seems to be what you are advocating, and c) is what the user actually wanted. Kev. > -Ken > > >> Kev. >> >> >>> -Ken >>> >>> Kevin Cameron wrote: >>> >>> >>>> To back up a bit in the discussion, I'd agree "<+" is a bit odd, but >>>> it's not that dissimilar to "+=" in C. The only objection I had was to >>>> extending the summing semantic to OOMRs and between analog blocks for >>>> potentials, which is why I suggested using "<++" to make that case >>>> explicit. Likewise I would have no problem with introducing a >>>> non-summing operator (say "<=") if that makes it clearer to users what >>>> is going on, that would then probably require another operator to match >>>> the "<++" (say "<=+") for symmetry. Given that modelers then use "<=" >>>> instead of "<+", why would they expect any summing of potential >>>> contributions for OOMRs or between blocks when using "<="? >>>> >>>> I think re-using operators from other languages would be a bad idea >>>> unless they do exactly the same thing. >>>> >>>> Kev. >>>> >>>> Geoffrey.Coram wrote: >>>> >>>> >>>>> Marq - >>>>> In most cases, though, the distinction doesn't matter: >>>>> if you don't expect the contributions to accumulate, >>>>> then you write your model with a single contrib and >>>>> everything works fine; or you have multiple contribs >>>>> of complicated expressions, and for efficienct, you >>>>> don't want to compute the complicated expressions that >>>>> you don't need. It'd be odd to have >>>>> >>>>> I(br) <+ (some complicated expression); >>>>> if (off) >>>>> I(br) <+ 0; //does not set branch current to zero! >>>>> >>>>> If it's off (the idea is that the user wanted to turn >>>>> the current off), it seems that the user would have >>>>> wanted to bypass the complicated expression: >>>>> if (off) >>>>> I(br) <+ 0; >>>>> else >>>>> I(br) <+ (some complicated expression); >>>>> >>>>> >>>>> The curious nature of the contrib is mentioned explicitly >>>>> in my tutorials for writing Verilog-A compact models ... >>>>> >>>>> -Geoffrey >>>>> >>>>> >>>>> >>>>> Marq Kole wrote: >>>>> >>>>> >>>>> >>>>>> All, >>>>>> >>>>>> I would even say that most users starting to write models for >>>>>> Verilog-AMS are quite unaware of this. They write their models as >>>>>> though it were a simple assignment - only in rare cases or when they >>>>>> start to work on more complicated models will they start looking at >>>>>> the actual LRM text and discover the contribution behavior. The same >>>>>> goes for the implicit equations for that matter... >>>>>> >>>>>> Just my $0.02. >>>>>> >>>>>> >>>>>> >>>>>> >>>>> >>>>> >>>>> >>>> >>>> >>> >>> >> ------------------------------------------------------------------------ >> >> http://www.grfx.com <http://www.grfx.com>mailto:dkc_ f rom _grfx.com <mailto:dkc_ f rom _grfx.com> >> >> > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Apr 30 12:36:18 2007
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