Verilog-AMS meeting

Hi all,

I sent a meeting notification for today's meeting last night but it 
looks like nobody received a copy. Geoffrey alerted me to this today and 
I realized I haven't got my own copy back. Not sure what happened.

I have attached the original notification email that i sent across, but 
i guess its a bit late for most attendees in the US.

cheers,
Sri

-------- Original Message --------
Subject: Agenda for Verilog-AMS Committee Meeting - 10 May 2007
Date: Wed, 09 May 2007 23:50:41 +0530
From: Sri Chandra <sri.chandra@freescale.com>
Organization: Freescale Semiconductor Inc
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>


Date & Time: 10 May 2007
Call-In Details:
   USA Toll Free: 877-346-8823
   USA Toll: +1-203-320-0407
   Passcode: 602538


Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide


Agenda:
   - idt() analog operator proposal (Ken Kundert)
   - $table_model proposal (Patrick O'Halloran)
We will discuss the idt() proposal by Ken first followed by the
technical document on $table_model.

Ken,
Could you please confirm or upload the latest version of the idt()
proposal document needed for tomorrow's discussion on the ams website.

Regards,
Sri
-- 
Sri Chandra
Design Technology (Tools)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199


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