I am not sure if any of you aware of this, but there is a similar proposal on the table in the VHDL-AMS group: http://www.eda-stds.org/vhdl-ams/wwwpages_new/new_features.html http://www.eda-stds.org/vhdl-ams/ftp_files/extensions/TLU/requirements_tlu_modeling_in_vhdl-ams_2006-03.pdf It would be nice if the two "table_models" would be identical or very similar... Any suggestions on how to get the two groups talking to each other? Arpad =========================================== -----Original Message----- From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Kevin Cameron Sent: Thursday, May 10, 2007 9:59 AM To: verilog-ams@server.eda.org Subject: Re: $table_model() requirements Can we do this without requiring a file format, i.e. can the $table functions just work off arrays and leave it up to the user how they populate those arrays (from files)? - you could just generate the table model directly as Verilog-AMS source, no need for splitting it into a Verilog wrapper around a .dat file - less chance you'll get the wrong file (or not find it). Kev. ... >> >> Hi All, >> >> It's been a long time since we discussed improving the $table_model() >> function in LRM 2.3 so I thought it would be best to start by reviewing all >> of the requirements gathered from the reflector and from users. Slides >> attached. >> >> Regards, >> Patrick >> >> Patrick O'Halloran >> Tiburon Design Automation >> > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu May 10 11:55:18 2007
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