All,
I've just sent an updated version of
section 7 "Hierarchical Structures" to Geoffrey for upload to
the Verilog-AMS website. These updates reflect the final discussion results
as noted in the Verilog-AMS committee minutes of April 20.
By the way, will we have a conference
call this week?
Cheers,
Marq
Marq Kole
Domain Leader Robust Design
Research
NXP Semiconductors
Tel: +31 40 27 49051, Fax: +31 40 27 46276, Mobile: +31 6 387 48 389
High Tech Campus HTC-37.4.037, 5656 AE Eindhoven, The Netherlands
marq.kole@nxp.com, www.nxp.com
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Received on Wed Jun 6 07:40:57 2007