Verilog-AMS Committee Meeting - 14 June 2007

From: Sri Chandra <sri.chandra_at_.....>
Date: Wed Jun 13 2007 - 08:07:27 PDT
Date & Time: 14 June 2007

Call-In Details:
    USA Toll Free: 877-346-8823
    USA Toll: +1-203-320-0407
    Passcode: 602538

Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide


Agenda:
    - $table_model proposal (Patrick O'Halloran) (The updated version of 
the LRM documentation will be put into the website today)
    - Donation from Synopsys (Verilog-A examples from LRM)

Also, Dave is planning to integrate the idt() proposal from Ken which 
addresses some of the oustanding issues, as part of chapter 4. Once that 
is integrated into the LRM document we will review it, possibly in the 
next call.


Outstanding Proposals:
    - Proposal on ACMI and changes related to support for multiple power
domains. Kevin has already submitted a proposal on this and Cadence is
also planning to submit a proposal for this issue which also discusses
backward compatibility while addressing the open issue.
    - Chapter 11 on compiler directives
    - LRM2.3 edits for Chapter 8, Chapter 9
    - LRM2.3 edits for Annex chapters (Annex C)

cheers,
Sri

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Received on Wed Jun 13 08:07:53 2007

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