RE: LRM Committee Meeting Agenda - 21 June 2007

Hi Sri,

Unfortunately my updates will not be ready for the meeting in the morning.
Sorry for the late notice.

Regards,
Patrick

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf
Of Sri Chandra
Sent: Wednesday, June 20, 2007 11:46 AM
To: Verilog-AMS LRM Committee
Subject: LRM Committee Meeting Agenda - 21 June 2007


Hi all,

We can go through Patrick's final version on $table_model based on 
comments from the meeting last week.

Date & Time: 21 June 2007

Call-In Details:
    USA Toll Free: 877-346-8823
    USA Toll: +1-203-320-0407
    Passcode: 602538

Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide

I will be traveling tomorrow and would not be able to make it to the 
call. I wanted to discuss the donation from synopsys for Verilog-A examples.

Just putting a plan for next few calls, we can look at the following:
   - Annex E (spice syntax - Marq)
   - idt proposal (chapter 4 - Dave)
   - compiler directives (chapter 11 - Graham)
   - Chapter 8 (mixed signal - dave)
   - Chapter 9 (scheduling semantics - cadence)

in the above order.

Martin - any update on the proposal from Cadence on handling multiple 
power supplies and related ACMI issues?

cheers.
Sri


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