Verilog-AMS Committee Meeting - 5th July 2007

Hi all,

Date & Time: 5th July 2007

Call-In Details:
    USA Toll Free: 877-346-8823
    USA Toll: +1-203-320-0407
    Passcode: 602538

Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide

Agenda:
   - Annex E updates
   - idt proposal (chapter 4 - Ken/Dave)

Just putting a plan for next few calls, we can look at the following:
   - compiler directives (chapter 11 - Graham)
   - Chapter 8 (mixed signal - dave)
   - Chapter 9 (scheduling semantics - cadence)

Martin - any update on the proposal from Cadence on handling multiple 
power supplies and related ACMI issues? Once we know whether there is 
another proposal on handling power domains as part of connect modules, 
which you mentioned Cadence had without regressing backward 
compatibility we can decide how to proceed and review the proposals 
available.

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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