Re: current discussion documents

Geoffrey,

Then my recollection has been fuzzier still, as what you say does ring a
bell. :-)

Another reason for putting them back in again might also be that the role
of a model card could easily be played by a paramset. If a paramset
provides the required parameter values for such a device (such as level,
type, etc.) would it be necessary to require a model card to use these
devices? This also allows the use of paramsets for SPICE built-in device
models such as BSIM4 for which there is no (official) Verilog-A code.

Anyway, I wasn't expecting this version of Annex E to be the last one.

Cheers,
Marq




                                                                       
                                                                       
                                                                       
                                                                        To
                                       Marq Kole <marq.kole@nxp.com>   
                                                                        cc
     "Geoffrey.Coram"                  verilog-ams                     
     <geoffrey.coram@anal              <verilog-ams@eda-stds.org>      
     og.com>                                                       Subject
                                       Re: current discussion documents
     15-08-2007 16:11                                       Classification
                                                                       
                                                                       
                                                                       
                                                                       
                                                                       
                                                                       
                                                                       




My recollection of the discussion is somewhat fuzzy, but:
I thought we wanted diode, mosfet, etc. left *in* the table,
because the table lists the port/terminal names and order
along with the "instance" parameters.

Eg, we want to standardize the connections that would be
made in the example:
     vertNPN Q1 (vcc, b1, e, vcc);

Table E.1 used to say that the ports were c, b, e, s
(in that order) and that one could specify a value for
the parameter area.

-Geoffrey


Marq Kole wrote:
> All,
>
> I've also updated Annex E of the LRM and Geoffrey Coram has been so kind
> to put it on the Verilog-AMS website. You can find it at:
>
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_spice.pdf
>
> The changes are largely related to section E.3:
> - Table E.1 has been changed to describe the behavior of the SPICE
> models in terms of their parameters.
> - Also in Table E.1 the device models for diode, mosfet, etc. have been
> removed because they require a model card.
> - And also in Table E.1 the dc, mag, and phase parameters of the SPICE
> sources have been removed.
> - Table E.2 that explained the model parameters for the sources has been
> removed, as that information is now in the behavioral description of
> Table E.1.
> - Finally, for section E.3.3 on name scoping I have taken over
> recommendations from Martin O'Leary for handling name clashes between
> SPICE and Verilog-AMS.
>
> If the issues with chapter 11 persist, we could review Annex E instead.
>
> Cheers,
> Marq
>

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