Hi Dave, That's one for Martin, I did $table_model() updates only, Patrick -----Original Message----- From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of David Miller Sent: Tuesday, August 21, 2007 12:36 PM To: patrick@tiburon-da.com; Verilog-AMS LRM Committee Subject: Question regarding Chap 10.5 vs 10.6 Hi Patrick, just wondering what the reason was we have both "Chapter 10.5 File input-output system tasks and fuctions - Vnew" "Chapter 10.6 File input-output system tasks and fuctions - Vold" Can we just delete Chapter 10.6? Dave -- ===================================== -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 ===================================== -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Aug 21 12:48:07 2007
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