inconsistency with SystemVerilog in sections 3, 4

 
In versions of sections 3 and 4 on the web site, I noticed that the
concatenation operator {} is being used to create array literals. This
is inconsistent with Verilog and SystemVerilog. I believe that this is
not what the concatenation operator is meant for.

In SystemVerilog array literals are created using '{ }. {} has another
meaning.

Removing this inconsistency would require that we update the examples in
section 3,4 and perhaps other sections as well as rework section 4.1.13
which, I believe, defines and uses the concatenation operator
incorrectly.

4.1.13 says that 
"A concatenation is used for joining scalar elements into a compound
element. The
concatenation shall be expressed using the brace characters ({ }), with
commas separating
the expressions within. A concatenation can be made up of other
concatenations which
can then be flattened into a single compound element."

However from Verilog-HDL 5.1.14, the concatenation looks to join groups
of bits into a single group of bits when used on bits.

For SystemVerilog LRM the concatenation joins groups of strings into a
single string when used on strings.

Hence from Verilog-HDL, SystemVerilog the concatenation operation does
not create compound elements but scalar elements.

Thanks,
--Martin

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