RE: suggestion

This exists in SystemVerilog.

Shalom 

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Scott Cranston
> Sent: Wednesday, August 29, 2007 3:36 PM
> To: Ken Kundert; verilog-AMS LRM Committee
> Subject: RE: suggestion
> 
> What you really want is a way to specify time absolutely, correct?
> 
> Something like #(1ns) where the 1ns is not scaled.
> 
> That seems like a clearer way to do what you want.
> 
>    -- Scott
> 
> 
> >>>>-----Original Message-----
> >>>>From: owner-verilog-ams@eda.org
> >>>>[mailto:owner-verilog-ams@eda.org] On Behalf Of Ken Kundert
> >>>>Sent: Tuesday, August 28, 2007 11:44 PM
> >>>>To: verilog-AMS LRM Committee
> >>>>Subject: suggestion
> >>>>
> >>>>All,
> >>>>    It would be very handy to have access to the `timescale value 
> >>>>from within a model so that we can write delays in terms of time 
> >>>>rather than ticks.
> >>>>
> >>>>Just to throw something out, say $tick returns the length 
> of a tick 
> >>>>in seconds. Then one can use it in the digital portion of 
> the model 
> >>>>as in the following example (a d flip-flop that implements 1n of 
> >>>>delay regardless of how `timescale was specified) ...
> >>>>
> >>>>
> >>>>parameter real td = 1ns;
> >>>>...
> >>>>
> >>>>always @(posedge clk) begin
> >>>>    q = #(td/$tick) d;
> >>>>end
> >>>>
> >>>>-Ken
> >>>>
> >>>>--
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> >>>>
> >>>>
> 
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