Re: FW: [sv-bc] 'inside' on real operands

I've never seen a need for this for compact models in Verilog-A.

I could imagine a behavioral model that measured an analog quantity
and wanted to know if it was in a range around say 1.8V or around 3.3V
or some other set of disjoint ranges, but I'd expect the model to do
different things for each range, so "inside" wouldn't be the right
operator.  While "inside" could be useful, it's not up there in the
top 10.

-Geoffrey



Bresticker, Shalom wrote:
> Here's a question for you.
> 
> I'm attaching a description of the 'inside' operator.
> 
> Thanks,
> 
> Shalom
> 
> 
> -----Original Message-----
> From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com]
> Sent: Monday, September 10, 2007 6:48 PM
> To: 'Jonathan Bromley'; 'Geoffrey.Coram'; Alsop, Thomas R
> Cc: Bresticker, Shalom; 'sv-bc'
> Subject: RE: [sv-bc] 'inside' on real operands
> 
> 
> Would using reals with the inside operator be useful for Verilog-AMS?  
> If not, I agree with prohibiting reals as operands of inside.  If the 
> Verilog-AMS committee sees this as useful, then we should define the 
> behavior and any caveats.
> 
> Stu

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