minutes Verilog-AMS committee meeting

All,

Here are the minutes of the conference call of the Verilog-AMS
standardization meeting of October 18, 2007.

Particpatring in the call:
- David Miller, Freescale
- Martin O'Leary, Cadence
- Marek Mierzwinski, Tiburon
- Marq Kole, NXP

Review of Annex C
- some minor typo's and English language items were fixed throughout the
document
- Geoffrey already made some changes to the document, i.e. changed all
references to the IEEE 1364-2001 to the current IEEE 1364-2005 standard,
and added table C-3 in section C.18 containing the changes from 2.1 to 2.2.
- in section C.2 the second bullet on reg-based string variables was
dropped in anticipation on an email sent to the reflector on October 16
regarding the need to have section 2.6 on strings in section 2 as this is a
literal copy from section 3.6 of the IEEE 1364-2005. This can be reinstated
if the discussion on that email turns out differently.
- in the same section an addition was made to first bullet to also exclude
the use of the question mark character in numbers as a replacement of x and
z.
- in section C.16 an addition was made to have a Verilog-A implementation
able to legally include disciplines.vams standard include file.
- in section C.18  table C-4 was added. Some items from section 10 were
still missing so these need to be added.

David requested that section C.18 is made into a separate annex and is not
restricted to the analog-only items. Marq will send the frame source of
Annex C to David to create an Annex H. The tables C-3 and C-4 will be part
of this, where table C-4 will be extended with the mixed-signal items. An
additional column in this table shall make clear whether a change applies
to the Verilog-A subset. Section C.18 in annex C will then be just a
pointer to new Annex H.

Another request was to move the `default_function_type_analog compiler
directive described in section C.11 to the obsolete functionality of
section C.19. This item is only needed for backward compatibility with
Verilog-A 1.0, not for any of 2.x standards. Instead of removing it, it
will just be marked obsolete.

Finally, if any of the items mentioned in section C.19 are encountered the
Verilog-A/Verilog-AMS code, a warning shall be issued.

[Actually, section C.19 is not restricted to the analog subset so should
actually move to new Annex H or have its own annex.]

Marq will make the changes and post a new version next week.

[The notes below are from Martin]

After this, we went through corrections to section 10 (systasks) that
Martin is planning to make. We can review these next week if necessary.

The changes are:
- fixed typo about $write not being supported in analog context and $writeb
etc being supported in analog context.
- removal of 10.6 as older version of IO section 10.5 and adding.
- changing all the subsection refs in 10.2 due to 10.6 being removed.
- add note about multi-channel file description and file descriptor being
different ways to open.
- clearly stated that for a mulitiple analysis simulation, that files
opened in a write mode in the first analysis are appended to in the
following analyses as this is more consistent with existing
implementations.

[Martin also noticed that the latest version of merged_systasks on the /pub
(V1.9) and the latest frame of that section given to Martin by Dave Miller
is missing changes from V1.3, V1.4, V1.5. This is because Martin gave
Patrick V1.2 on which to do the interpolation work. Martin will merge the
changes from V1.3, V1.4, V1.5 with V1.9]

Cheers,
Marq
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