minutes Verilog-AMS committee meeting November 1, 2007

All,

Here are the minutes of the conference call of the Verilog-AMS
standardization meeting of November 1, 2007.

Participating in the call:
- Geoffrey Coram, Analog Devices
- David Miller, Freescale
- Martin O'Leary, Cadence
- Junwei Hou, Cadence
- Marq Kole, NXP

Status:
- Dave has received all frame source documents for the standard from Sri
and will integrate them into a first full draft as soon as he has received
chapter 10;
- Martin will try to update chapter 10 over the weekend and send an updated
frame source to both Geoffrey and Dave;
- When the full first draft is ready everyone who authored a chapter should
verify that the impact of the changes in the chapter on other parts of the
LRM are correctly presented. If they are not a proposal should be made on
how to handle the impact;
- the new section containing the changes from previous versions as well as
the obsolete syntax will be in Annex H. The Glossary will become Annex I as
that should be at the end of the LRM document.
- The LRMs so far lack an index although some indexing information is
present in the current frame source. When the full LRM drafts are reviewed
entries for the index should be part of the review process so the next
version of the document will have a proper index.
- Marq will have a look at the relation between the IEEE 1364-2005 sections
on VPI and the chapters 12 and 13 of the Verilog-AMS 2.2 LRM and report any
collisions.

Junwei has updated chapter 9 with the review comments from the previous
time - this document was uploaded to the reflector during the call and
reviewed. The following comments were made:
- in section 9.3.1 an analog_initial block is mentioned - did we decide to
do that? Previous discussions on the reflector seemed to indicate that it
was not needed.
It turns out that there is a use case for an analog initial block in
mixed-signal simulation. At this moment it is not possible for the digital
blocks to read an analog variable (through an OOMR) at initialization as
the analog simulation only starts to run after the digital has performed
its initialization. By using an analog initial block the analog part of a
mixed-signal design can be initialized such that the digital can use such
initial values.
Similarly, the analog cannot open a file to read such values from - a feat
that cannot be achieved either by providing an initializer when a variable
is declared, apart from the fact that providing an initializer for an
analog variable is not allowed.
The analog initial_step event is only executed after the digital simulator
has handled its time=0 events.

The order for mixed signal simulation now comes down to:
1. (analog) nodeset
2. (analog) analog initial block(s)
3. (digital) initial block(s) / always block(s)
4. (analog) analog block including initial_step global event
The nodeset and analog initial block together are the analog
initialization.

- a request was made that either Martin or Junwei provide some information
on the analog initial block that can be discussed on the email reflector.
- the text in section 9.3.1 uses analog_initial, but a better situation
would be to have an initial block inside an analog block - this would
prevent having to create a new keyword analog_initial. This was agreed;
- in section 9.3.2 near the end of the first paragraph the statement
@initial_step should become @(initial_step);
- in section 9.3.2 in the second paragraph the text "state (include analog
and digital)" should become "initialization state (including analog and
digital)";
- a description of the analog initial block would need to be added to
chapter 6 - Martin will include this in the impact document;

Next week we hopefully will have a look at the first full draft of the
Verilog-AMS 2.3 LRM! We will also have the call at a different time due to
Daylight Savings Time - it'll be in the invitation next week.

Best regards,
Marq
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