minutes Verilog-AMS committee meeting November 15, 2007

Verilog-AMS Standardization Conference Call

November 15, 2007

Attending:
- David Miller, Freescale
- Martin O'Leary, Cadence
- Boris Troyanovsky, Tiburon
- Marq Kole, NXP

Status of the LRM:
   A proposal for the analog initial block has not been submitted yet, it
   will probably be available in 2 weeks time. The outset will be that it
   has the same restrictions as user-defined functions, and that it will be
   executed right after the nodeset has been done.
   Here are a couple of items discussed during the call regarding the
   properties of the analog initial block:
      We do not allow contribution statements in the analog initial block
      as at that time the solver has not been started yet. However a
      voltage probe should be possible – it will return the value of a
      nodeset for that voltage or 0 in case there was no nodeset.
      In a DC sweep analysis is the analog initial block reevaluated if a
      parameter changes due to the sweep? The analog initial block should
      be sensitive to any changes in parameters that are used inside the
      block. It has the same sensitivity to parameter changes as a
      localparam statement.
      Multiple analog initial blocks are allowed but follow the same
      structure as regular analog blocks: at elaboration time they are
      concatenated into a single analog initial block in the order in which
      they appear in the input text.
      Should there be an analog final block in addition to an analog
      initial block, for instance for closing a file at the end of an
      analysis? The feeling is no: there is a use case for the analog
      initial block that cannot be covered by the analog initial_step
      event. There is no such use case (yet) for the analog final block.
      Closing a file can be performed in an analog final_step event -- even
      though that final step event can be executed multiple times before
      the solution has converged, the actual closing of the file should be
      postponed until the final_step event solution has been accepted.
   The syntax (Annex A) is not up to date in the current vamsbook 2.3 draft
   A document -- Sri did contact Graham a few weeks ago on this. Before the
   syntax is handled over to Stu it should be updated by Graham to reflect
   the changes since the last update of the Annex A document.
   Section 4.5.2 discusses the handling of nodesets and the fact that the
   solution found in the previous operating point is carried over to the
   next: a statement r = r + 1 in the body of an analog block will nicely
   iterate, while the same statement in an initial_step event will not
   iterate. The text does mention independent DC analyses, but it is not
   sufficiently clear if this also applies to nested DC sweeps. This should
   be clarified in the text.
   defparam has not been deprecated in this LRM -- it retains it for the
   same reason as 1364-2005. Once SystemVerilog deprecates the defparam
   statement, we will follow suit.

Status of the Impact Documents:
   Martin went through the impact document for section 9 on system tasks:
      SystemVerilog strings have been added to LRM 2.3
      driver update functions have been removed from section 7
      (mixed-signal)
      DC solution for mixed signal is now described in section 8
      preference for Verilog HDL version of the math functions needs to be
      added to annex C.
      deprecation of disicpline logic and $realtime need to be added to
      Annex H.
      return values of $fopen are 32-bit multi-channel descriptors or
      32-bit file descriptors depending on the call arguments
      glossary should be extended with a description of context
   Marq went through the impact document for section 6 on hierarchy:
      Genvars as described in section 3 can be used for generate constructs
      as well
      The item on analog blocks in section 6 that comes from the former
      section 6 needs to get the notion of multiple analog blocks
      The syntax in annex A should be updated with the generate constructs
      Annex C should mention the support of the the generate constructs in
      analog-only context.
   From now on any edits -- including those mentioned in the impact
   documents -- should be performed by Stu Sutherland as Technical Author.
   The only exception might be the updates of Annex A for which Graham
   Helwig probably has the most up-to-date version. It is not clear whether
   Stu has this latest version.

Next meeting
   Due to Thanksgiving weekend next week in the US the call will be
   skipped. The next Verilog-AMS Standardization conference call will be on
   November 29, 2007.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.