Minute of meeting: 6 Dec 2007

Minutes of meeting: 6 December, 9:30p PST

Marq Kole, NXP
Sri Chandra, Freescale
Dave Miller, Freescale
Boris Troyanovsky, Tiburon
Martin O'Leary, Cadence
Stu Sutherland, Sutherland-HDL
Dave Cronauer, Synopsys
Graham Helwig, ASTC

Discussion on hierarchical names proposal
   * Implementation of out-of-module hierarchical access of variables 
unclear - returning last accepted timepoint vs latest value of 
newton-raphson iteration.
   * Evaluation of instance where the variable belongs is not guaranteed 
when we look at iteration values
   * Ambiguity with strobe values on last accepted values
   * From the discussion it seemed very unclear what a good use case for 
this feature would be. Dave has used it to open global file descriptors 
which can now be resolved also with analog initial block proposal.
   * Sent mail to reflector and gather feedback for the need for 
allowing hierarchically access of out of module variables.

BNF
   - All syntax mismatches (individual syntax boxes in each of the 
sections) will be updated with syntax in Annex A. Stu has already been 
doing this work as part of his draft_2 work.
   - no change in wreal syntax required in BNF. wreal has not yet been 
included as part of net_type in system verilog. There was some 
discussions and they have deferred the change.
   - changes to syntax A.2.7 (inclusion of discipline_identifier to task 
declaration) is referred anywhere in the body. Suggestion was to add a 
small section in Chapter 4 after UDF, section 4.7: Task declaration and 
mention that task declarations cannot be used in the analog context.
   - analog_loop_generate_statement will be put in a separate BNF by 
itself as part of A.4.3
   - Create new syntax item for analog_global_events which will just 
include initial_step and final_step events and refer to this syntax in 
Section 5.9.2
   - no change required for analog_function_*_statement in BNF and body
   - Update concatenation syntax to be consistent with system verilog. 
ie. use `{ for denoting concatenation of values. This will be part of 
the deprecated syntax in LRM2.3 (same as systemverilog which changed 
from { to `{). Also refer to this syntax in section 4.1.13
   - Section 4.4 and 4.5.1 to include appropriate syntax in the sections 
from A.8.2
   - change reference to A.6.9 to be A.8.7 in syntax 2-2 (Stu has 
already addressed this issue as part of draft2 edits)

Other:
   - Stu will use minutes to track changes until draft_2 edits are done 
and completed. It was decided that the above BNF updates will be 
included for draft_2.
   - Post draft_2 any changes to documentation will go through the 
mantis database.

Next Meeting: 13 Dec 2007

cheers,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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