From what i understand of the process, for creating an 1800.1 standard I think we have to set up a working group to initiate & request for a PAR (Project Authorization Request?). I saw a documentation on the same at https://development.standards.ieee.org/cgi-bin/NesCOM/myP_par?start. We need to get approval of the standard from the Design Automation Standards Committee. So i guess once we release LRM2.3 we need to form a working group that will work on the PAR and the subsequent approval of the 1800.1 standard. I also spoke with Karen saying that we need participation of somebody from SV to be part of this working group and participate in the PAR development and she will check with her committee to see whether there are any volunteers on that. Regards, Sri Geoffrey.Coram wrote: > Kevin - > LRM 2.3 work is focused on synchronization with 1364-2005, > instead of the outdated -1995 that the previous AMS LRMs > are based on. I view this as a necessary precondition to > transferring AMS to the IEEE. > > I have yet to see anyone from the P1800 working group approach > the Accellera AMS to set up 1800.1 (a la 1076.1 VHDL-AMS); the > closest we came was 1800-XC, which sort of treated AMS as an > external language to be interfaced with. > > -Geoffrey > > > > Kevin Cameron wrote: >> Marq, >> >> I was under the impression that a goal of the committee (from its >> inception) was to create a unified AMS HDL, and since most Verilog >> work is now at the IEEE, AMS was to be transferred to the IEEE P1800 >> effort as soon as possible. Are you saying that is not the goal, and >> as an end user you (and NXP) are happy to see multiple versions of >> Verilog and a fractured analog/digital design community? >> >> The original Verilog-AMS Design Objectives Document >> <http://eda.org/verilog-ams/htmlpages/dod.html> is well out-of-date >> now, it might be a good idea to create a new one so that we all know >> what the current goals are. >> >> Kev. >> >> Marq Kole wrote: >>> >>> Hi Joginder, >>> >>> Standardization efforts are currently performed within the Accellera >>> standardization organization, although there is a long term intent to >>> have Verilog-AMS become an IEEE standard, we're currently not working >>> on that. We do however try to conform as much as possible to IEEE >>> standards with the upcoming 2.3 release of the standard. This will >>> make the transition from an Accellera standard into an IEEE standard >>> simpler. The fully approved 2.3 standard can reasonably be expected >>> somewhere in the middle of next year. On the public documents site of >>> the Verilog-AMS standardization website >>> (www.eda-stds.org/verilog-ams) draft versions of the various chapters >>> and an initial draft of the standard can be found. >>> >>> Verilog-AMS is very well supported in the commercial EDA offerings >>> from many companies: the big EDA companies all have their >>> mixed-signal simulation environment supporting Verilog-AMS, mostly >>> adhering to the 2.2 standard. There are also offerings from smaller >>> companies specializing in mixed signal simulation solutions. Next to >>> that the analog subset known as Verilog-A is supported in nearly all >>> analog, SPICE-like simulators on the market. >>> >>> I hope this answers your questions, but feel free to ask if anything >>> is unclear. >>> >>> Best regards, >>> Marq >>> >>> >>> Inactive hide details for "Joginder Singh" >>> <joginder.singh@gmail.com>"Joginder Singh" <joginder.singh@gmail.com> >>> >>> >>> *"Joginder Singh" <joginder.singh@gmail.com>* >>> >>> Sent by: >>> owner-verilog-ams@server.eda.org >>> >>> 07-12-2007 13:55 >>> >>> >>> >>> To >>> >>> "verilog-AMS LRM Committee" <verilog-ams@server.eda.org> >>> >>> cc >>> >>> "Joginder Singh" <joginder.singh@gmail.com> >>> >>> Subject >>> >>> IEEE std on Verilog AMS >>> >>> Classification >>> >>> >>> >>> >>> >>> Hi All, >>> >>> I understand there is significant effort going on for statndardization >>> Verilog AMS. And it is in use in design projects. I am curious to know >>> as to how soon will we have an IEEE standard >>> finalized/approved/published. Could someone from standardization >>> committee please throw some light on this? >>> >>> Other things I would appreciate knowing are how good is the support by >>> existing simulators and its popularity among analog/ams designers. >>> Well, that is a wider question but it always has made me curious. >>> -- >>> Regards, >>> Joginder. >>> >>> -- >>> This message has been scanned for viruses and >>> dangerous content by MailScanner, and is >>> believed to be clean. >>> >>> >>> >>> -- >>> This message has been scanned for viruses and >>> dangerous content by *MailScanner* <http://www.mailscanner.info/>*, >>> and is >>> believed to be clean. * >>> >> * >> >> * >> >> ------------------------------------------------------------------------ >> * <http://www.grfx.com>mailto:dkc_ f rom _grfx.com <mailto:dkc_ f rom _grfx.com>* >> >> * >> -- >> This message has been scanned for viruses and >> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is >> believed to be clean. * > -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Dec 12 22:34:18 2007
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