Draft2 version of the LRM

Hi all,

Stu has sent over the draft2 version of the LRM and I have requested
Dave Miller to upload it in the website, and hopefully it would be
accessible from there in a day or so.

The essential changes from draftA that was uploaded previously was to
make the LRM into an IEEE compatible format. Stu has also made lot of
notes in the LRM, some informational and some requiring the attention of
the committee which we will go through as part of the review process of
draft2. I have already given some feedback to Stu with regards to wrong 
cross-references due to new/deleted sections but this will be fixed as 
part of the next revision.

I have attached some of the observations/corrections i sent over to Stu 
with regards to the cross-references with this email which we can go 
through as part of the review to ensure the correctness of the same. We 
will start review of this document from the upcoming Verilog-AMS meeting.

   - note on page 31, the reference should be 3.4.3 which talks about 
units and description. There is no sub-sections called 3.1.1, 3.2.3 and 
3.4.3.1 as i just noticed :). It should be updated for both the bullet 
points.

   - For the note on Page 45, it should be 3.6.1.2 as the reference for 
the nature attributes.

   - On page 159, the reference to var is for an identifier, which is 
not declared and hence will not compile :(. I guess we need to change it 
to some other identifier name if its an SV keyword. Probably a 
declaration like "real analogVar" should be there and all reference to 
this analogVar. We can discuss this as part of committee.

   - The reference is section 8.3.1 page 193, should be 3.6.3.2 which 
explains the nodeset details.

   - In section 9.3, page 213, the references are to cluases 9.2 and 9.3 
respectively.

   - In section 9.5.1.1 page 217, the reference should be to Clause 8. 
One chapter got deleted (original chapter 5) and this reference was not 
correctly updated.

   - In section 9.14 the reference should be to 4.2 and table 4-17.


Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199


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