RE: Draft 2 is now available - 7.10

In digital SV, the LRM says,
 
"Ports can always be represented as declared objects connected as
follows:

- If an input port, then a continuous assignment from an outside
expression to a local (input) net or variables

- If an output port, then a continuous assignment from a local output
expression to an outside net or variables"

and

"Each port connection shall be a continuous assignment of source to
sink, where one connected item shall be a signal source and the other
shall be a signal sink. The assignment shall be a continuous assignment
from source to sink for input or output ports."

An exception is where port collapsing occurs.

"all the ports through a hierarchy down to a process or primitive" would
be a series connection of continuous assignments, unless port collapsing
occurs.

Shalom


________________________________

	From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Kevin Cameron
	Sent: Sunday, January 06, 2008 11:14 AM
	To: Verilog-AMS LRM Committee
	Subject: Re: Draft 2 is now available - 7.10
	
	

	Section 7.10 says -
	

		A driver of a signal is a process which assigns a value
to the signal, or a connection of the signal to
		an output port of a module instance or simulation
primitive.
		

	I think it should just say -
	

		A driver of a signal is a process which assigns a value
to the signal, or a connection of the signal to
		an output port of a simulation primitive.
		

	Output ports on regular modules are not in themselves drivers
just connections to drivers. The implication of the current text is that
you would count all the ports through a hierarchy down to a process or
primitive as separate drivers.
	
	Kev.
	
	
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