In the latest draft we discuss string variables in clause 2.7.1 and 2.7.2 But here we are referring to the old digital style of using a register data type. We have also added in the System Verilog style of having an explicit "string" variable type and we discuss this in clause 3.3. I don't think we want to mention string registers at all, and we should simply remove clause 2.7.1 and 2.7.2. As a result, clause 2.7 will just discuss what is a string literal and the special characters in strings (the existing clause 2.7.3) Clause 3.3 will remain as is and discuss the new string variable type. Cheers... Dave -- ===================================== -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 ===================================== -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 17 10:53:29 2008
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