If you are interested in another approach to how to define simulator independent statistical modeling for an AMS-HDL you should take a look at SAE J2748 - VHDL-AMS Statistical Analysis Package. This is available at www.sae.org and the reference implementation is available at http://links.sae.org/J2748. This was created with the automotive industry for doing Monte-Carlo in VHDL-AMS. You might find helpful. Regards David David W. Smith Synopsys Scientist Synopsys, Inc. Synopsys Technology Park 2025 NW Cornelius Pass Road Hillsboro, OR 97124 Voice: 503.547.6467 Main: 503.547.6000 Cell: 503.560.5389 FAX: 503.547.6906 Email: david.smith@synopsys.com http://www.synopsys.com Saber Accelerates Robust Design Predictable. Repeatable. Reliable. Proven. -----Original Message----- From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram Sent: Friday, February 08, 2008 3:18 AM To: Sri Chandra Cc: Bresticker, Shalom; Verilog-AMS LRM Committee; Neil.Korpusik@sun.com Subject: Re: [Fwd: Minutes of Verilog-AMS meeting - 31 Jan 2008] Hi, Sri - Note that the $rdist_ functions are AMS-only, so there should be no problem letting the seed argument to these functions be a parameter. The intended use is in paramsets, and I don't think $random (which returns a 32-bit integer) is particularly useful in that context. As to the comment that the constant version not being used: the Compact Model Council asks me each time it meets how AMS is doing at sorting out problems with Monte-Carlo specifications; the CMC is eager to have a simulator-independent way to specify this information, and Verilog-AMS could be that way. So, while the constant version (of $rdist_) is not being used presently, it's because of other deficiencies in the LRM (mentioned in my earlier e-mail), not because the feature has no demand. -Geoffrey Sri Chandra wrote: > Hi all, > > The issue of distribution functions taking constant arguments was > discussed as part of the committee meeting today. Stu suggested there > are few options which we can pursue without deviating from SystemVerilog > and still keeping the feature in the language. > > Option #1: We can restrict it semantically to ensure that the constant > arguments are used only in paramset declarations and any other usage of > distribution functions will have integer variables instead of the > constant counterpart. This feature i think was mainly introduced to > support for paramset for RHS assignments for parameters which needed > constant expressions > > Option #2: We can extend the distribution function to have an optional > second argument, which can be the constant_expression which is just an > extension to the current syntax and hence will not be in conflict. Of > course in this case we need to detail what it means if a constant > expression is specified and also has the variable as the first argument. > > Option #3: Have an equivalent function for the distribution functions > amsrand or absrand which extends the current distribution function to > take in parameter and constant expressions and we can keep the current > random and distribution functions the same as the system verilog > counterpart. Apparently SV has already done this by having urand (?) as > an extension to 1364 which will return an unsigned number. > > Option #4: There was a feeling that the constant version is not being > used. I wasn't sure about this and if that is the case, the opinion was > to drop this deviation and just keep it consistent with the digital syntax. > > > Regards, > Sri > > > Bresticker, Shalom wrote: >> There is a schedule problem. It would require permission from the P1800 >> Working Group. >> >> Shalom >>> -----Original Message----- >>> From: Sri Chandra [mailto:sri.chandra@FREESCALE.COM] Sent: Thursday, >>> February 07, 2008 7:40 PM >>> To: Bresticker, Shalom >>> Cc: Geoffrey.Coram; Verilog-AMS LRM Committee >>> Subject: Re: [Fwd: Minutes of Verilog-AMS meeting - 31 Jan 2008] >>> >>> Can we impress upon the SV committee to extend the current syntax? I >>> know it might be a difficult task but thought will ask rather than >>> assume. >>> >>> Regards, >>> Sri >>> >>> Bresticker, Shalom wrote: >>>> No. >>>> >>>>> Is there any plans to include constant seed argument >>>>> (parameter) to P1800 standards? >>> -- >>> Srikanth Chandrasekaran >>> Design Technology (Tools Development) >>> Freescale Semiconductor Inc. >>> T:+91-120-439 5000 p:x3824 f: x5199 >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> >> > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Feb 8 08:53:10 2008
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