Declaring that two disciplines are incompatible

All,
     Is there a way in Verilog-AMS to declare that two disciplines are 
incompatible and should never be interconnected. For example, say I 
declare two discipline, logic18 and logic32, one for 1.8V logic and the 
other for 3.2V logic. Can I use the resolveto construct to declare them 
incompatible?

discipline logic18
     domain discrete;
enddiscipline
discipline logic32
     domain discrete;
enddiscipline
connectrules myRules
     connect logic18, logic32 resolveto ;
endconnectrules

Currently I don't think the language has the ability to do this, but it 
seems like a nice feature. This way I could prevent logic from different 
supply domains from interconnected by accident.

-Ken

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