Dave, Thanks for the suggestion. Unfortunately, connect modules are only an option when there are two disciplines, and one is discrete and the other is continuous. In my example, I purposely gave two discrete domains. As such, they are naturally compatible. I need a way that works for disciplines that are compatible (either two discrete, or two compatible continuous). -Ken David Sharrit wrote: > Perhaps a workaround would be to create a dummy connect module, that doesn't > actually connect anything and possibly just prints out a warning, and then > have the two incompatible disciplines resolve to that. > > David > >> -----Original Message----- >> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On >> Behalf Of Ken Kundert >> Sent: Saturday, February 16, 2008 7:36 PM >> To: Verilog-AMS LRM Committee >> Subject: Declaring that two disciplines are incompatible >> >> All, >> Is there a way in Verilog-AMS to declare that two disciplines are >> incompatible and should never be interconnected. For example, say I >> declare two discipline, logic18 and logic32, one for 1.8V logic and the >> other for 3.2V logic. Can I use the resolveto construct to declare them >> incompatible? >> >> discipline logic18 >> domain discrete; >> enddiscipline >> discipline logic32 >> domain discrete; >> enddiscipline >> connectrules myRules >> connect logic18, logic32 resolveto ; >> endconnectrules >> >> Currently I don't think the language has the ability to do this, but it >> seems like a nice feature. This way I could prevent logic from different >> supply domains from interconnected by accident. >> >> -Ken >> >> -- >> This message has been scanned for viruses and >> dangerous content by MailScanner, and is >> believed to be clean. > > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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