RE: initialization order

Hi Xavier, Junwei, all,

Seems you've unearthed a small inconsistency in the LRM: what is call the
initialization state in section 8.3.2 is called the initialization phase in
8.3.1. Seems to me that we should make this consistent: initialization
phase seems like the right wording here.

   For mixed-signal DC analysis, the processes of the analog DC analysis
   and the digital simulation at time 0 are executed iteratively, starting
   with the initialization statephase (including analog and digital)
   defined in circuit initialization (8.3.1).

By the way, there is still room for interpretation here, so I would suggest
that the text of 8.3.1 make the order of first the analog initial block,
then the digital initial block for time 0.

   The initialization phase of mixed-signal simulation is the process of
   initializing the circuit state for analysis tasks such as DC, transient,
   and AC. It is a one time execution of nodeset statements (3.4.3.2), and
   then the procedures in the analog initial block, and then the procedures
   in the Verilog initial block for time 0.

Can this still be changed in Draft 3?

Cheers,
Marq


> Hi Junwei,
>
> thanks for your answer. I had forgotten there was now a dedicated
> analog initialization section, so I had a hard time understanding
> what "the initialization state (including analog and digital)"
> meant. Now it's clearer.
>
> Thanks,
>     Xav
>
> On Thu, 2008-03-06 at 17:28 -0800, Junwei Hou wrote:
> Hi Xavier,
>
> Sorry for replying late as I was on vacation. The short answer is
> yes, the digital initial block is run first. Here is the relevant
> descriptions in the LRM2.3:
>
> Section 8.3.2 states:
> For mixed-signal DC analysis, the processes of the analog DC
> analysis and the digital simulation at time 0 are executed
> iteratively, starting with the initialization state (including
> analog and digital) defined in circuit initialization (8.3.1).
>
> Section 8.3.1 states:
> The initialization phase of mixed-signal simulation is the process
> of initializing the circuit state for analysis tasks such as DC,
> transient, and AC. It is a one time execution of nodeset statements
> (3.4.3.2), and then the procedures in analog initial block and
> Verilog initial block.
>
> Note that analog initial block is something new (and still open to
> be added to chapter 6) and equivalent to digital initial block,
> which is run before any analysis. Analog initial_step is part of an
> analysis such as DC in your example.
>
> Thanks,
> --Junwei
>
>
>
> owner-verilog-ams@server.eda.org wrote on 04-03-2008 18:37:34:
>
> > Hi again,
> >
> > does anyone have a hint of an answer on this question ?
> >
> > Thanks,
> >    Xav
> >
> > On Wed, 2008-02-27 at 16:00 +0100, Xavier Bestel wrote:
> > > Hi,
> > >
> > > when you have a design with both a initial block (digital) and an
> > > initial_step (in the analog block), is there a designated execution
> > > order ?
> > >
> > > Apparently, there's a Kundert testcase where there's a division by a
> > > digital signal, in the initial_step. That would implicitly mean that
the
> > > initial block should be ran first by the simulator.
> > >
> > > However I can't find any thace of this in the LRM. Could someone
> > > enlighten me please ?
> > >
> > > Thanks,
> > >
> > >    Xav
> >
> >
> > --
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