me either now.. jbd Jonathan David j.david@ieee.org jb_david@yahoo.com http://ieee-jbdavid.blogspot.com Mobile 408 390 2425 ----- Original Message ---- From: Kevin Cameron <Kevin.Cameron@truecircuits.com> To: Verilog-AMS LRM Committee <verilog-ams@eda.org> Sent: Wednesday, April 2, 2008 11:48:00 AM Subject: Re: Verilog-AMS committee meeting reminder - 3rd April 2008 Sri Chandra wrote: > 06:30am US Pacific > ... Not going to make that. > > Agenda: > * Review of draft3 from chapter 5 onwards. I didn't get any feedback on on the connect module placement issue - http://www.verilog.org/mantis/view.php?id=2343 Does anyone have problems with making the changes? Kev. > > Marq - Would it be possible for you to chair the call tomorrow please? > I may not be able to join the call. > > cheers, > Sri -- True Circuits Inc. - http://www.truecircuits.com Tel: (650) 949 3400 Ext 3415 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Apr 3 01:49:39 2008
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