3.13.3 and 3.13.4 refer to "module block". I think these should be just "module". "module block" is not used elsewhere, nor in 1364. 3.13.4 says, "The hierarchical reference character (.) can be used to reference a net across the module boundary according to the rules specified in IEEE std 1364-2005 Verilog HDL." This looks just copy-pasted from 3.13.4. Should it be "to reference a branch"? Regards, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6582 +972 54 721-1033 --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jun 3 02:33:00 2008
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