reducing warning messages

In developing Verilog-A compact models, I sometimes have to introduce
special syntax for one compiler to get the model to run, but the same
syntax causes trouble in another.

For example, ADMS likes to have attributes like
  (* type="instance" ask="yes" *)
but some compilers issue warnings to tell me that they don't recognize
the attributes "type" and "ask" -- perhaps in case I mis-typed some
attribute that they do recognize.

Once I have reviewed these warnings, I would like to suppress them when
I distribute the model for other users.  What is the correct mechanism
to suppress these warnings?

a) a command-line argument to the simulator: this is not ideal, because
    the user might need to review warnings for her own modules

b) a "magic comment" like //SUPPRESS_WARNINGS at the top of the file

c) an attribute like (* suppress_warnings *) module r3_cmc(n1,nc,n2);

d) a macro like `define suppress_warnings

These mechanisms won't be in the AMS LRM, but it would be nice to have
some simulator vendors agree.

-Geoffrey

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